TRACKING MECHANISM FOR WRITING TO A MEMORY CELL

• US 20150131391A1
• Filed: 01/22/2015
• Published: 05/14/2015
• Est. Priority Date: 07/27/2012
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: HSU, Kuoyuan (Peter), WANG, Bing, TAO, Derek C., TANG, Yukit, FAN, Kai
• Granted Patent: US 9,418,717 B2
• Time in Patent Office: Days
• US Class Current: 365/189.16
• CPC Class Codes: G11C 11/419 Read-write [R-W] circuits
• CPC Class Codes: G11C 7/12 Bit line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, equalising circuits, for bit lines
• CPC Class Codes: G11C 7/222 Clock generating, synchronizing or distributing circuits within memory device
• CPC Class Codes: G11C 7/227 Timing of memory operations based on dummy memory elements or replica circuits

Abstract

A circuit includes a write driver, a data circuit, a memory cell, a tracking write buffer, a tracking write driver, and a tracking cell. The circuit is configured that, during a write operation of the memory cell based on a clock signal, the write driver circuit is configured to generate a write control signal to control the memory cell; the data circuit is configured to provide write data to the memory cell; the tracking write buffer is configured to generate a tracking write control signal; and the tracking write driver is configured to generate a tracking write data signal to be transferred to the tracking cell. The tracking cell is configured to adjust a signal at a first node of the tracking cell based on a logical value of the tracking write data signal in response to the tracking write control signal.

Claims

1. A circuit comprising:

a write driver;

a data circuit;

a memory cell;

a tracking write buffer;

a tracking write driver; and

a tracking cell,

wherein the circuit is configured that, during a write operation of the memory cell based on a clock signal,

the write driver circuit is configured to generate a write control signal on a write control line to control the memory cell;

the data circuit is configured to provide write data to the memory cell on a write data line;

the tracking write buffer is configured to generate a tracking write control signal on a tracking write control line to control the tracking cell;

the tracking write driver is configured to generate a tracking write data signal on a tracking write data line to be transferred to the tracking cell; and

the tracking cell is configured

to adjust a signal at a first node of the tracking cell toward having a logical value based on a logical value of the tracking write data signal in response to the tracking write control signal; and

to generate a tracking signal based on the signal at the first node of the tracking cell.

2. The circuit of claim 1, wherein the tracking cell comprises:

a second node;

a third node configured to carry an operational voltage;

a fourth node configured to carry a reference voltage;

a first P-type transistor between the first node and the third node;

a first N-type transistor between the first node and the fourth node, gates of the first P-type transistor and the first N-type transistor and the second node being electrically coupled together;

a second P-type transistor between the second node and the third node;

a second N-type transistor between the second node and the fourth node, gates of the second P-type transistor and the second N-type transistor and the first node being electrically coupled together; and

a third N-type transistor between the tracking write data line and the first node, a gate of the third N-type transistor being electrically coupled with the tracking write control line.

3. The circuit of claim 2, wherein the tracking cell further comprises:

a fourth N-type transistor between the third node and the second node, a gate of the fourth N-type transistor being electrically coupled with the tracking write control line.

4. The circuit of claim 2, wherein the tracking cell further comprises:

a third P-type transistor between the third node and the first P-type transistor, a gate of the third P-type transistor being electrically coupled with the second node; and

a fourth P-type transistor between the third node and the second P-type transistor, a gate of the fourth P-type transistor being electrically coupled with the first node.

5. The circuit of claim 2, wherein the tracking cell further comprises:

a first inverter having an input terminal and an output terminal, the input terminal of the first inverter being electrically coupled with the first node, and the output terminal of the first inverter being configured to carry the tracking signal.

6. The circuit of claim 2, wherein the tracking cell further comprises:

a fifth node;

a sixth node electrically coupled with the second node;

a fifth P-type transistor between the fifth node and the third node;

a fifth N-type transistor between the fifth node and the fourth node, gates of the fifth P-type transistor and the fifth N-type transistor and the sixth node being electrically coupled together;

a sixth P-type transistor between the sixth node and the third node;

a sixth N-type transistor between the sixth node and the fourth node, gates of the sixth P-type transistor and the sixth N-type transistor and the fifth node being electrically coupled together;

a seventh N-type transistor between the tracking write data line and the fifth node, a gate of the seventh N-type transistor being electrically coupled with the tracking write control line; and

an eighth N-type transistor between the third node and the sixth node, a gate of the eighth N-type transistor being electrically coupled with the tracking write control line.

7. The circuit of claim 6, wherein the tracking cell further comprises:

a second inverter having an input terminal and an output terminal, the input terminal of the second inverter being electrically coupled with the fifth node, and the output terminal of the second inverter being electrically coupled with the output terminal of the first inverter.

8. The circuit of claim 2, wherein the tracking cell further comprises:

a ninth N-type transistor between the second node and the fourth node, a gate of the ninth N-type transistor being configured to be controlled based on a reset signal.

9. The circuit of claim 1, further comprising:

a clock generator circuit configured to generate a reset signal based on the tacking signal.

10. A method of writing to a memory cell comprising:

based on a clock signal,

generating a first edge of a write control signal on a write control line of the memory cell;

setting a write data signal on a write data line of the memory cell to have a first value;

generating a first edge of a tracking write control signal on a tracking write control line; and

setting a tracking write data signal on a tracking write data line to have a second value;

responsive to the tracking write control signal, adjust a signal at a first node of a tracking cell to have a third value based on the second value of the tracking write data signal;

generating a reset signal based on the signal at the first node of the tracking cell; and

based on the reset signal,

generating a second edge of the write control signal.

11. The method of claim 10, further comprising:

based on the reset signal,

generating a second edge of the tracking write control signal; and

setting the first node of the tracking cell to have a fourth value different from the third value.

12. The method of claim 10, further comprising:

based on the reset signal,

setting the tracking write data signal on the tracking write data line to have a fifth value different from the second value.

13. The method of claim 10, further comprising

receiving the clock signal from outside of a memory macro having the memory cell.

14. The method of claim 10, wherein

the write control line is a write word line of a memory macro;

the write data line is a write bit line of the memory macro;

the tracking write control line is coupled with a first plurality of memory cells; and

the tracking write data line is coupled with a second plurality of memory cells.

15. A tracking circuit in a memory macro comprising:

a clock generator circuit;

a tracking cell comprising a first node;

a tracking write buffer;

a tracking write control line coupled with the tracking cell and the tracking write buffer;

a tracking write driver; and

a tracking write data line coupled with the tracking cell and the tracking write driver,

wherein

the clock generator circuit is configured to receive a first clock signal, and, based on the first clock signal, generate a first edge of a second clock signal;

the tracking write buffer, based on the first edge of the second clock signal, is configured to generate a first edge of a tracking write control signal on the tracking write control line;

the tracking write driver, based on the first edge of the second clock signal, is configured to set a tracking write data signal on the tracking write data line to a first logical value; and

the tracking cell is configured to be written at the first node with the first logical value from the tracking write data signal in response to the tracking write control signal.

16. The tracking circuit of claim 15, wherein

the tracking cell is configured to generate a tracking signal based on a signal at the first node;

the clock generator circuit is configured generate a second edge of the second clock signal based on the tracking signal.

17. The tracking circuit of claim 16, wherein

the tracking write buffer, based on the second edge of the second clock signal, is configured to generate a second edge of the tracking write control signal on the tracking write control line;

and

the tracking write driver, based on the second edge of the second clock signal, is configured to set the tracking write data signal on the tracking write data line to a second logical value different from the first logical value.

18. The tracking circuit of claim 15, wherein the tracking cell comprises:

a second node;

a third node configured to carry an operational voltage;

a fourth node configured to carry a reference voltage;

a first P-type transistor between the first node and the third node;

a first N-type transistor between the first node and the fourth node, gates of the first P-type transistor and the first N-type transistor and the second node being electrically coupled together;

a second P-type transistor between the second node and the third node;

a second N-type transistor between the second node and the fourth node, gates of the second P-type transistor and the second N-type transistor and the first node being electrically coupled together;

a third N-type transistor between the tracking write data line and the first node, a gate of the third N-type transistor being electrically coupled with the tracking write control line; and

a fourth N-type transistor between the third node and the second node, a gate of the fourth N-type transistor being electrically coupled with the tracking write control line.

19. The tracking circuit of claim 18, wherein the tracking cell further comprises:

a first inverter having an input terminal and an output terminal, the input terminal of the first inverter being electrically coupled with the first node, and the output terminal of the first inverter being configured to carry a tracking signal.

20. The tracking circuit of claim 18, wherein the tracking cell further comprises:

a fifth N-type transistor between the second node and the fourth node, a gate of the fifth N-type transistor being configured to be controlled based on a reset signal.