CONSTRUCTING VIRTUAL MOTHERBOARDS AND VIRTUAL STORAGE DEVICES

• US 20150134824A1
• Filed: 11/12/2013
• Published: 05/14/2015
• Est. Priority Date: 11/12/2013
• Status: Active Grant

• Current Assignee: Microsoft Technology Licensing LLC (Microsoft Corporation)
• Original Assignee: Microsoft Corporation
• Inventors: Mickens, James Williamson, Farasat, Ali Raza
• Granted Patent: US 9,553,822 B2
• Time in Patent Office: Days
• US Class Current: 709/226
• CPC Class Codes: G06F 2009/4557 Distribution of virtual machine instances; Migration and load balancing
• CPC Class Codes: G06F 2009/45579 I/O management, e.g. providing access to device drivers or storage
• CPC Class Codes: G06F 9/45558 Hypervisor-specific management and integration aspects
• CPC Class Codes: G06F 9/5027 the resource being a machine, e.g. CPUs, Servers, Terminals
• CPC Class Codes: G06F 9/5077 Logical partitioning of resources; Management or configuration of virtualized resources specific details on emulation or internal functioning of virtual machines G06F9/455
• CPC Class Codes: H04L 47/70 Admission control; Resource allocation
• CPC Class Codes: H04L 67/60 Scheduling or organising the servicing of application requests, e.g. requests for application data transmissions using the analysis and optimisation of the required network resources admission control or resource allocation H04L47/70

Abstract

Described herein are various technologies pertaining to a computing system architecture that facilitates construction of virtual motherboards and virtual storage devices. A computing system includes a plurality of computing nodes and a plurality of storage nodes, where the computing nodes are disaggregated from the storage nodes. The computing nodes include respective system on chip modules. The computing nodes and the storage nodes are communicatively coupled by way of a full bisection bandwidth network, where each storage node is allocated network bandwidth that at least matches the maximum input/output speed of the storage node. Responsive to receipt of a client request, computing nodes are allocated to the client and exposed to an application of the client as a motherboard. Likewise, storage nodes are allocated to the client and exposed to the application of the client as a larger storage device.

Claims

1. A computing system that is configured to service requests of a plurality of clients, the computing system comprising:

a plurality of System on Chip (SoC) modules, each SoC module in the plurality of SoC modules comprising;

a respective microprocessor core;

a respective memory module that is accessed by the respective microprocessor core; and

a respective network interface that interfaces a respective SoC module to at least one other device, wherein the respective microprocessor core, the respective local memory, and the respective network interface are formed on a common substrate;

a plurality of data storage nodes remotely situated from the plurality of SoC modules; and

a network that communicatively couples the plurality of SoC modules with the plurality of data storage nodes, that data storage nodes allocated respective network bandwidths based upon respective input/output speeds of the plurality of data storage nodes.

2. The computing system of claim 1, the plurality of SoC modules being homogeneous.

3. The computing system of claim 1, the network being a full bisection bandwidth network.

4. The computing system of claim 1, wherein each data storage node in the plurality of data storage nodes is allocated a respective network bandwidth that at least matches a respective maximum input/output speed of a respective data storage node.

5. The computing system of claim 1, further comprising a stager computing device that receives a request from a client from amongst the plurality of clients, the request indicating an amount of processing resources, the stager computing device allocating a subset of SoC modules from the plurality of SoC modules to the client responsive to receipt of the request.

6. The computing system of claim 5, wherein the request is for an odd number of microprocessor cores, and wherein the stager computing device allocates the subset of SoC modules such that the odd number of microprocessor cores are allocated to the client.

7. The computing system of claim 5, wherein the request from the client further indicates an amount of data storage resources, the stager computing device allocating a subset of data storage nodes from the plurality of data storage nodes to the client responsive to receipt of the request.

8. The computing system of claim 5, wherein the subset of SoC modules executes an application of the client.

9. The computing system of claim 1, further comprising a plurality of local storage modules that are respectively coupled to the plurality of SoC modules by way of respective buses.

10. The computing system of claim 9, the plurality of local storage modules comprising flash memory modules.

11. The computing system of claim 1, the plurality of data storage nodes comprising at least one of a hard disk, a solid state drive, or a tape drive.

12. A method, comprising:

receiving, at a computing system, a request from a client of the computing system, the request comprising data that indicates processing resources for executing an application for the client; and

responsive to receiving the request, identifying a plurality of unallocated SoC modules of the computing system, the plurality of unallocated SoC modules comprising the processing resources indicated in the request, each SoC module in the plurality of SoC modules comprising;

a respective microprocessor core;

a respective local memory module that is accessed by the respective microprocessor core; and

a respective network interface that interfaces a respective SoC module to at least one other device, the respective microprocessor core, the respective local memory module, and the respective network interface formed on a common substrate; and

responsive to identifying the plurality of SoC modules, allocating the plurality of SoC modules to the client for executing the application.

13. The method of claim 12, further comprising exposing the plurality of SoC modules to the client as a virtual non-uniform memory access (NUMA) motherboard.

14. The method of claim 13, wherein the data in the request indicates data storage resources for executing the application for the client, the method further comprising:

responsive to receiving the request, identifying at least one unallocated storage node that comprises the data storage resources indicated in the request; and

responsive to identifying the at least one unallocated storage node, allocating the at least one storage node to the client.

15. The method of claim 14, further comprising providing address space that is mapped to the at least one storage node to the plurality of SoC modules, wherein the SoC modules transmit data to and retrieve data from the at least one storage node by way of the address space when executing the application for the client.

16. The method of claim 15, wherein a network connection between the plurality of SoC modules and the at least one storage node has a bandwidth that corresponds to an aggregate I/O speed of the at least one storage node.

17. The method of claim 16, wherein the network connection is a portion of a full bisection bandwidth network.

18. The method of claim 12, wherein each SoC module in the plurality of SoC modules has a respective local memory attached thereto by way of a respective bus.

19. The method of claim 12, wherein the request indicates that an odd number of microprocessor cores are desired by the client, and wherein allocating the plurality of SoC modules comprises allocating the odd number of microprocessor cores to the client.

20. A computing system comprising:

a plurality of System on Chip (SoC) modules, each SoC module in the plurality of SoC modules comprises;

a respective microprocessor;

a respective a respective local memory that is accessed by the respective microprocessor core; and

a respective network interface that interfaces a respective SoC module that comprises the respective network interface to at least one other device in the computing system, the respective microprocessor core, the respective local memory, and the respective network interface residing on a single chip;

a plurality of storage nodes that are communicatively coupleable to the plurality of SoC modules over a full bisection bandwidth network; and

a stager computing device that receives a request for computing resources and storage resources from a client and, responsive to receiving the request, allocates a plurality of unallocated SoC modules and a plurality of unallocated storage nodes to the client, wherein bandwidth of a network connection between the plurality of unallocated SoC modules and the plurality of unallocated storage nodes is at least an aggregate of maximum I/O speeds of the plurality of unallocated storage nodes.