Decoupling Host and Device Address Maps for a Peripheral Component Interconnect Express Controller
First Claim
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1. A controller apparatus comprising:
- one or more hardware engines;
memory connected to the one or more hardware engines;
one or more host ports connected to the one or more hardware engines, configured to connect to one or more host devices; and
one or more device ports connected to the one or more hardware engines, configured to connect to one or more peripheral component interconnect express devices,wherein the one or more hardware engines are configured to;
determine a transaction size;
allocate a virtual buffer, associated with one or more memory addresses in the peripheral component interconnect device, in a virtual memory according to the transaction size; and
associate the virtual buffer with a scatter/gather list element, associated with a memory address in a host.
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Abstract
A controller includes a virtual memory mapped to device-side Peripheral component interconnect express address space includes virtual buffers allocation for each data transfer. Each virtual buffer is associated with a scatter/gather list entry in a host memory. The controller executes direct transfers between Peripheral component interconnect express devices and host memory without introducing address mapping dependencies between the host and device domains.
9 Citations
20 Claims
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1. A controller apparatus comprising:
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one or more hardware engines; memory connected to the one or more hardware engines; one or more host ports connected to the one or more hardware engines, configured to connect to one or more host devices; and one or more device ports connected to the one or more hardware engines, configured to connect to one or more peripheral component interconnect express devices, wherein the one or more hardware engines are configured to; determine a transaction size; allocate a virtual buffer, associated with one or more memory addresses in the peripheral component interconnect device, in a virtual memory according to the transaction size; and associate the virtual buffer with a scatter/gather list element, associated with a memory address in a host. - View Dependent Claims (2, 3, 4, 5, 6, 7)
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8. A method for mapping peripheral component interconnect device addresses to host addresses, comprising:
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determining a transaction size; allocating a virtual buffer in a virtual memory according to the transaction size; and associating the virtual buffer with a scatter/gather list element, wherein; the virtual buffer is associated with one or more virtual memory addresses provided to the peripheral component interconnect device; and the scatter/gather list entry is associated with a memory address in the host. - View Dependent Claims (9, 10, 11, 12, 13, 14)
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15. A redundant array of independent disks data storage device comprising:
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a plurality of peripheral component interconnect data storage devices; and a controller configured to control access between the plurality of peripheral component interconnect data storage devices and one or more hosts, comprising; one or more hardware engines; memory connected to the one or more hardware engines; one or more host ports connected to the one or more hardware engines, configured to connect to one or more host devices; and one or more device ports connected to the one or more hardware engines and connected to the one or more peripheral component interconnect express devices, wherein; the one or more hardware engines are configured to; determine a transaction size; allocate a virtual buffer, associated with one or more memory addresses in the peripheral component interconnect device, in a virtual memory according to the transaction size; and associate the virtual buffer with a scatter/gather list element, associated with a memory address in a host. - View Dependent Claims (16, 17, 18, 19, 20)
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Specification