METHOD AND SYSTEM FOR IMPROVING ERROR CORRECTION IN DATA STORAGE

• US 20150135033A1
• Filed: 11/08/2013
• Published: 05/14/2015
• Est. Priority Date: 11/08/2013
• Status: Active Grant

• Current Assignee: SanDisk Technologies LLC (Western Digital Corporation)
• Original Assignee: SanDisk Enterprise IP LLC (Western Digital Corporation)
• Inventors: Ellis, Robert W., Higgins, James M., Dancho, Mark
• Granted Patent: US 9,747,157 B2
• Time in Patent Office: Days
• US Class Current: 714/763
• CPC Class Codes: G06F 11/10 Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's
• CPC Class Codes: G06F 11/1048 using arrangements adapted for a specific error detection or correction feature
• CPC Class Codes: G11C 11/4074 Power supply or voltage generation circuits, e.g. bias voltage generators, substrate voltage generators, back-up power, power control circuits
• CPC Class Codes: G11C 16/0483 comprising cells having several storage transistors connected in series

Abstract

A method of operation of a data storage system includes: monitoring a data interface bus, the monitoring by a non-volatile memory controller; activating a zero bit counter for detecting a ratio of 1'"'"'s to 0'"'"'s on the data interface bus; and adjusting a threshold voltage (V_th), based on the ratio of the 1'"'"'s to the 0'"'"'s from the zero bit counter, by the non-volatile memory controller.

Claims

1. A method for improving error correction in a data storage system comprising:

monitoring a data interface bus, the monitoring by a non-volatile memory controller;

activating a zero bit counter for detecting a ratio of 1'"'"'s to 0'"'"'s on the data interface bus; and

adjusting a threshold voltage (V_th), based on the ratio of the 1'"'"'s to the 0'"'"'s from the zero bit counter, by the non-volatile memory controller.

2. The method as claimed in claim 1 further comprising reading a non-volatile memory device by the non-volatile memory controller.

3. The method as claimed in claim 1 wherein activating the zero bit counter includes detecting an uncorrectable error correction code (ECC) error by an error correction module.

4. The method as claimed in claim 1 further comprising:

accessing a counter interface register coupled to the zero bit counter for conveying the ratio of the 1'"'"'s to the 0'"'"'s on the data interface bus; and

wherein;

adjusting the threshold voltage (V_th) includes estimating an amount and direction of the adjusting by a processor module.

5. The method as claimed in claim 1 further comprising accessing a non-volatile memory device by the non-volatile memory controller for driving the data interface bus.

6. A method of operation of a data storage system comprising:

monitoring a data interface bus, the monitoring by a non-volatile memory controller, by an error correction module;

activating a zero bit counter, for detecting a ratio of 1'"'"'s to 0'"'"'s on the data interface bus, coupled between the non-volatile memory controller and the error correction module; and

adjusting a threshold voltage (V_th), based on the ratio of the 1'"'"'s to the 0'"'"'s from the zero bit counter, by the non-volatile memory controller including preventing an uncorrectable error correction code (ECC) error on a re-read.

7. The method as claimed in claim 6 further comprising reading a non-volatile memory device by the non-volatile memory controller including adjusting the threshold voltage (V_th) without detecting the uncorrectable error correction code (ECC) error.

8. The method as claimed in claim 6 wherein activating the zero bit counter includes detecting an uncorrectable error correction code (ECC) error by an error correction module including tagging an erase block in a non-volatile memory device as erased, recycled, spare, or retired.

9. The method as claimed in claim 6 further comprising:

accessing a counter interface register coupled to the zero bit counter for conveying the ratio of the 1'"'"'s to the 0'"'"'s, of an erase block in a non-volatile memory device, accumulated from the data interface bus; and

wherein;

adjusting the threshold voltage (V_th) includes estimating an amount and direction of the adjusting by a processor module including re-reading the erase block in the non-volatile memory device.

10. The method as claimed in claim 6 further comprising accessing a non-volatile memory device by the non-volatile memory controller for driving the data interface bus including coupling a snoop connection to the data interface bus without adding latency between the non-volatile memory controller and the error correction module.

11. A data storage system comprising:

a non-volatile memory controller for driving a data interface bus;

a zero bit counter, coupled to the data interface bus, for detecting a ratio of 1'"'"'s to 0'"'"'s on the data interface bus; and

a threshold voltage (V_th) adjusted by the non-volatile memory controller based on the ratio of the 1'"'"'s to the 0'"'"'s from the zero bit counter.

12. The system as claimed in claim 11 further comprising a non-volatile memory device coupled to and read by the non-volatile memory controller.

13. The system as claimed in claim 11 wherein the zero bit counter, coupled to the data interface bus, and an error correction module coupled to the data interface bus for detecting an uncorrectable error correction code (ECC) error.

14. The system as claimed in claim 11 further comprising:

a counter interface register coupled to the zero bit counter for conveying the ratio of the 1'"'"'s to the 0'"'"'s accumulated from the data interface bus; and

a processor module, coupled to the counter interface register, for estimating an amount and direction of adjustment to the threshold voltage (V_th).

15. The system as claimed in claim 11 further comprising a non-volatile memory device accessed by the non-volatile memory controller for driving the data interface bus.

16. The system as claimed in claim 11 further comprising:

an error correction module, coupled to the non-volatile memory controller, for monitoring the data interface bus; and

wherein;

the zero bit counter, coupled to the data interface bus, between the error correction module and the non-volatile memory controller.

17. The system as claimed in claim 16 further comprising a non-volatile memory device coupled to and read by the non-volatile memory controller includes the threshold voltage (V_th) adjusted without an uncorrectable error correction code (ECC) error detected by the error correction module.

18. The system as claimed in claim 16 wherein the zero bit counter, coupled to the data interface bus, and an error correction module coupled to the data interface bus for detecting an uncorrectable error correction code (ECC) error includes a non-volatile memory device coupled to the non-volatile memory controller for tagging an erase block as erased, recycled, spare, or retired.

19. The system as claimed in claim 16 further comprising:

a counter interface register coupled to the zero bit counter for conveying the ratio of the 1'"'"'s to the 0'"'"'s, of an erase block in a non-volatile memory device, accumulated from the data interface bus; and

a processor module, coupled to the counter interface register, for estimating an amount and direction of adjustment to the threshold voltage (V_th) including the erase block in the non-volatile memory device re-read through the data interface bus.

20. The system as claimed in claim 16 further comprising a non-volatile memory device accessed by the non-volatile memory controller for driving the data interface bus includes a snoop connection coupled to the data interface bus without adding latency between the non-volatile memory controller and the error correction module.