DISPLAY PANEL

• US 20150137117A1
• Filed: 11/06/2014
• Published: 05/21/2015
• Est. Priority Date: 11/15/2013
• Status: Abandoned Application

• Current Assignee: InnoLux Corporation
• Original Assignee: InnoLux Corporation
• Inventors: TSAI, Chia-Hao
• Application Number:
  US14/535,029
• Publication Number:
  US 20150137117A1
• Time in Patent Office: Days
• US Class Current: 257/43
• CPC Class Codes: H01L 27/1225 with semiconductor materials not belonging to the group IV of the periodic table, e.g. InGaZnO
• CPC Class Codes: H01L 27/124 with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits wiring structures per se H01L23/52
• CPC Class Codes: H01L 27/1244 for preventing breakage, peeling or short circuiting
• CPC Class Codes: H01L 29/41733 for thin film transistors with insulated gate
• CPC Class Codes: H01L 29/78618 characterised by the drain or the source properties, e.g. the doping structure, the composition, the sectional shape or the contact structure silicide contacts, electrodes in general H01L29/458
• CPC Class Codes: H01L 29/7869 having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate
• CPC Class Codes: H01L 29/78696 characterised by the structure of the channel, e.g. multichannel, transverse or longitudinal shape, length or width, doping structure, or the overlap or alignment between the channel and the gate, the source or the drain, or the contacting structure of the channel H01L29/78612 takes precedence; transistors having a drain offset region or a lightly doped drain [LDD] H01L29/78621

Abstract

A display panel includes a first substrate and a plurality of pixels disposed on the first substrate. At least one of the pixels includes a gate line region, an active layer, an etch stop layer, a first and second source/drain layer. The gate line region is disposed on the first substrate and includes a first region and a second region. The first region includes a first portion having a first width and the second region includes a second portion having a second width. The first width is greater than the second width. The active layer is disposed on the gate line region and includes a channel region disposed on the first region. The etch stop layer and first and second source/drain layers are disposed on the active layer, and the portion of the active layer between the first and second source/drain layers is the channel region.

Claims

1. A display panel, comprising:

a first substrate;

a plurality of pixels disposed on the first substrate, at least one of the pixels comprising;

a gate line region disposed on the first substrate and extended along a first direction and including a first region and a second region, wherein the first region includes a first portion and the second region includes a second portion, the first portion and the second portion have a first width and a second width along a second direction, respectively, the first direction is perpendicular to the second direction and the first width is greater than the second width;

an active layer disposed on the gate line region and including a channel region disposed on the first portion;

an etch stop layer disposed on the active layer; and

a first source/drain layer and a second source/drain layer disposed on the active layer and connected to the active layer, wherein the portion of the active layer between the first source/drain layer and the second source/drain layer is the channel region;

a second substrate disposed on the first substrate; and

a display medium disposed between the first and second substrates.

2. The display panel as recited in claim 1, wherein the active layer further includes a non-channel region, the second region further has a first opening, and the non-channel region is disposed on the first opening.

3. The display panel as recited in claim 1, wherein the active layer further includes a non-channel region, which is disposed on the second portion.

4. The display panel as recited in claim 3, wherein the second region further has a second opening.

5. The display panel as recited in claim 1, wherein the second width is 2 μ

m˜

20 μ

m.

6. The display panel as recited in claim 5, wherein the second width is 4 μ

m˜

15 μ

m.

7. A display panel, comprising:

a first substrate;

a plurality of pixels disposed on the first substrate, at least one of the pixels comprising;

a gate line region disposed on the first substrate and extended along a first direction;

an active layer disposed on the gate line region;

an etch stop layer disposed on the active layer and having a first via and a second via;

a first source/drain layer disposed on the active layer and disposed in the first via to connect to the active layer;

a second source/drain layer disposed on the active layer and disposed in the second via to connect to the active layer; and

a first insulation layer disposed on the first source/drain layer and the second source/drain layer and disposed in the first via;

a second substrate disposed on the first substrate; and

a display medium disposed between the first and second substrates.

8. The display panel as recited in claim 7, wherein the portion of the active layer between the first source/drain layer and the second source/drain layer is a channel region, the active layer further includes a non-channel region, and the portion of the first insulation layer disposed in the first via is disposed on the non-channel region.

9. The display panel as recited in claim 7, wherein at least one of the pixels further includes a pixel electrode layer disposed on the first insulation layer and in the second via.

10. The display panel as recited in claim 9, wherein the portion of the active layer between the first source/drain layer and the second source/drain layer is a channel region, the active layer further includes a non-channel region, and the portion of the pixel electrode layer disposed in the second via is disposed on the non-channel region.

11. The display panel as recited in claim 7, wherein the first source/drain layer has a third width of 5 μ

m˜

8.5 μ

m along the first direction.

12. A display panel, comprising:

a first substrate;

a plurality of pixels disposed on the first substrate, at least one of the pixels comprising;

a gate line region disposed on the first substrate and extended along a first direction;

an active layer disposed on the gate line region;

an etch stop layer disposed on the active layer and having a first via and a second via;

a first source/drain layer disposed on the active layer and disposed in the first via to connect to the active layer;

a second source/drain layer disposed on the active layer and disposed in the second via to connect to the active layer;

a first insulation layer disposed on the first source/drain layer and the second source/drain layer; and

a pixel electrode layer disposed on the first insulation layer and in the second via;

a second substrate disposed on the first substrate; and

a display medium disposed between the first and second substrates.

13. The display panel as recited in claim 12, wherein the portion of the active layer between the first source/drain layer and the second source/drain layer is a channel region, the active layer further includes a non-channel region, and the portion of the pixel electrode layer disposed in the second via is disposed on the non-channel region.

14. The display panel as recited in claim 12, wherein the first insulation layer is disposed in the first via.

15. The display panel as recited in claim 14, wherein the portion of the active layer between the first source/drain layer and the second source/drain layer is a channel region, the active layer further includes a non-channel region, and the portion of the first insulation layer disposed in the first via is disposed on the non-channel region.

16. The display panel as recited in claim 12, wherein the second source/drain layer has a fourth width of 5 μ

m˜

8.5 μ

m along the first direction.