Hybrid Domain Wall-Hall Cross Device

• US 20150137200A1
• Filed: 11/10/2014
• Published: 05/21/2015
• Est. Priority Date: 11/21/2013
• Status: Active Grant

• Current Assignee: The United States of America As Represented By The Secretary of Agriculture
• Original Assignee: The Government Of The United States Of America, As Represented By The Secretary Of The Navy
• Inventors: Johnson, Mark B., Malec, Christopher
• Granted Patent: US 9,276,197 B2
• Time in Patent Office: Days
• US Class Current: 257/295
• CPC Class Codes: G11C 11/161 details concerning the memory cell structure, e.g. the layers of the ferromagnetic memory cell
• CPC Class Codes: G11C 11/1675 Writing or programming circuits or methods
• CPC Class Codes: G11C 11/18 using Hall-effect devices
• CPC Class Codes: H10N 52/101 Semiconductor Hall-effect devices
• CPC Class Codes: H10N 52/80 Constructional details

Abstract

A hybrid domain wall Hall cross device consists of a semiconductor Hall cross having a top surface and a pair of arms intersecting at a center region, and a ferromagnetic wire fabricated on the top surface, electrically isolated from the Hall cross, and having a constriction proximate to the center of the Hall cross. The device provides a magnetoelectronic MRAM storage cell with improved performance characteristics. Binary storage is associated with a trapped domain wall having one of two stable orientations. The bit state can be written using current driven domain wall motion. This is a STT process in which the write current is applied to a thin film, low impedance wire. Heating is minimized and no wear-out mechanism is known to exist.

Claims

1. A hybrid domain wall Hall cross device, comprising:

a semiconductor Hall cross having a top surface and a pair of arms intersecting at a center region;

and a ferromagnetic wire fabricated on the top surface, electrically isolated from the Hall cross, and having a constriction proximate to the center of the Hall cross.

2. The device of claim 1, wherein the Hall cross has a size in the range of from 10 nm to 1 micron, the wire has a width in the range of from 10 nm to 500 nm, the wire is continuous and extends from a first end of the Hall cross to a second opposing end of the Hall cross, and the wire terminates at each such end in an electrode.

3. The device of claim 1, wherein the Hall cross is an InAs heterostructure.

4. The device of claim 3, wherein the heterostructure is InAs/InAlSb.

5. The device of claim 1, wherein the Hall cross is Si or Ge or a compound of either Si or Ge.

6. A hybrid domain wall Hall cross memory device, comprising:

a semiconductor Hall cross having a top surface and a pair of arms intersecting at a center region;

and a ferromagnetic wire fabricated on the top surface, electrically isolated from the Hall cross, having a constriction proximate to the center of the Hall cross, and having at least two configurable and stable magnetization orientation states corresponding to two different values of a data item stored in said device, and covering a portion of the top surface such that a fringe magnetic field having two states and configured substantially normal to the top surface can be generated by an edge portion of the ferromagnetic wire; and

wherein two different electrical signals, each corresponding to a different one of the two different data values, can be generated in response to the two fringe magnetization field states acting on an electrical current flowing in the top surface.

7. A nonvolatile memory array comprising a plurality of hybrid domain wall Hall cross memory cells, wherein each said cell comprises:

a semiconductor Hall cross having a top surface and a pair of arms intersecting at a center region; and

a ferromagnetic wire fabricated on the top surface, electrically isolated from the Hall cross, having a constriction proximate to the center of the Hall cross, and having at least two configurable and stable magnetization orientation states corresponding to two different values of a data item stored in said device, and covering a portion of the top surface such that a fringe magnetic field having two states and configured substantially normal to the top surface can be generated by an edge portion of the ferromagnetic wire; and

wherein two different electrical signals, each corresponding to a different one of the two different data values, can be generated in response to the two fringe magnetization field states acting on an electrical current flowing in the top surface.

8. The nonvolatile memory array of claim 7, wherein at least one field effect transistor is incorporated in each cell to isolate the cell from the array.

9. The nonvolatile memory array of claim 7, wherein at least one field effect transistor is incorporated in each cell to control the write current applied to the FW of each cell.