UNDOPED EPITAXIAL LAYER FOR JUNCTION ISOLATION IN A FIN FIELD EFFECT TRANSISTOR (FINFET) DEVICE

• US 20150137237A1
• Filed: 11/21/2013
• Published: 05/21/2015
• Est. Priority Date: 11/21/2013
• Status: Abandoned Application

• Current Assignee: GlobalFoundries, Inc.
• Original Assignee: GlobalFoundries, Inc.
• Inventors: Jacob, Ajey Poovannummoottil, Akarvardar, Murat K.
• Application Number:
  US14/086,199
• Publication Number:
  US 20150137237A1
• Time in Patent Office: Days
• US Class Current: 257/347
• CPC Class Codes: H01L 21/76224 using trench refilling with dielectric materials trench filling with polycristalline silicon H01L21/763; together with vertical isolation, e.g. trench refilling in a SOI substrate H01L21/76264
• CPC Class Codes: H01L 29/0646 PN junctions
• CPC Class Codes: H01L 29/66795 with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/785 having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET

Abstract

Approaches for isolating source and drain regions in an integrated circuit (IC) device (e.g., a fin field effect transistor (FinFET)) are provided. Specifically, the FinFET device comprises a gate structure formed over a finned substrate; an isolation oxide beneath an active fin channel of the gate structure; an embedded source and a drain (S/D) formed adjacent the gate structure and the isolation oxide; and an undoped epitaxial (epi) layer between the embedded S/D and the gate structure. The device may further include an epitaxial (epi) bottom region of the embedded S/D, wherein the epi bottom region is counter doped to a polarity of the embedded S/D, and a set of implanted regions implanted beneath the epi bottom region, wherein the set of implanted regions is doped and the epi bottom region is undoped. In one approach, the embedded S/D comprises P++ doped Silicon Germanium (SiGe) for a p-channel metal-oxide-semiconductor field-effect transistor (PMOSFET) and N++ Silicon Nitride (SiN) for a n-channel metal-oxide-semiconductor field-effect transistor (NMOSFET).

Claims

1. A device comprising:

a gate structure formed over a finned substrate;

an embedded source and a drain (S/D) adjacent the gate structure; and

an undoped epitaxial (epi) layer between the embedded S/D and the gate structure.

2. The device of claim 1, further comprising an epi bottom region of the embedded S/D, the epi bottom region counter doped to a polarity of the embedded S/D.

3. The device of claim 2, further comprising an implanted region beneath the epi bottom region, wherein the implanted region is doped and the epi bottom region is undoped.

4. The device of claim 1, wherein the embedded S/D is doped.

5. The device according to claim 1, further comprising an isolation oxide beneath an active fin channel of the gate structure.

6. The device according to claim 1, the undoped epi layer extending beneath the embedded S/D.

7. A fin field effect transistor (FinFET) device having an undoped epitaxial layer for junction isolation, the FinFET device comprising:

a gate structure formed over a finned substrate;

an isolation oxide beneath an active fin channel of the gate structure;

an embedded source and a drain (S/D) formed adjacent the gate structure and the isolation oxide; and

an undoped epitaxial (epi) layer formed between the embedded S/D and the gate structure.

8. The FinFET device of claim 7, further comprising an epi bottom region of the embedded S/D, the epi bottom region counter doped to a polarity of the embedded S/D.

9. The FinFET device of claim 8, further comprising an implanted region beneath the epi bottom region, wherein the implanted region is doped and the epi bottom region is undoped.

10. The FinFET device of claim 7, wherein the embedded S/D is doped.

11. The device according to claim 7, the undoped epi layer extending beneath the embedded S/D.

12. A method for forming an undoped epitaxial layer for junction isolation in a fin field effect transistor (FinFET) device, the method comprising:

forming a gate structure over a finned substrate;

providing an isolation oxide beneath an active fin channel of the gate structure;

forming an embedded source and a drain (S/D) adjacent the gate structure and the isolation oxide; and

forming an undoped epitaxial (epi) layer between the embedded S/D and the gate structure.

13. The method of claim 12, further comprising forming an epi bottom region of the embedded S/D, the epi bottom region counter doped to a polarity of the embedded S/D.

14. The method of claim 13, further comprising implanting a set of implanted regions beneath the epi bottom region, wherein the set of implanted regions is doped and the epi bottom region undoped.

15. The method of claim 12, further comprising doping the embedded S/D.

16. The method according to claim 12, the undoped epi layer extending beneath the epi bottom region of the embedded S/D.

17. The method according to claim 12, further comprising:

forming a set of fins from a bulk Si;

depositing a shallow trench isolation (STI) material over the set of fins;

recessing the STI material to expose the set of fins; and

forming a spacer over each of the set of fins.

18. The method according to claim 17, further comprising performing a thermal oxidation to the FinFET device following deposition of the STI material over the set of fins.

19. The method according to claim 17, the forming the set of fins:

forming an epi SiGe layer over the bulk Si;

forming an epi Si layer over the epi SiGe; and

patterning a set of openings through the epi Si layer and the epi SiGe layer, and into the bulk silicon.

20. The method according to claim 17, the forming the set of fins from the substrate comprising:

patterning a set of openings into the bulk Si;

forming a SiN capping layer over each of the set of fins; and

etching the bulk Si between each of the set of fins.