SEMICONDUCTOR PACKAGE HAVING HEAT SPREADER

• US 20150137345A1
• Filed: 10/01/2014
• Published: 05/21/2015
• Est. Priority Date: 11/21/2013
• Status: Abandoned Application

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Samsung Electronics Co. Ltd.
• Inventors: CHOI, Eun-Kyoung, HAN, Sang-Uk, CHO, Tae-Je
• Application Number:
  US14/504,309
• Publication Number:
  US 20150137345A1
• Time in Patent Office: Days
• US Class Current: 257/713
• CPC Class Codes: H01L 2224/16145 the bodies being stacked
• CPC Class Codes: H01L 2224/16225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/32225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/73204 the bump connector being embedded into the layer connector
• CPC Class Codes: H01L 2225/06513 Bump or bump-like direct electrical connections between devices, e.g. flip-chip connection, solder bumps
• CPC Class Codes: H01L 2225/06517 Bump or bump-like direct electrical connections from device to substrate
• CPC Class Codes: H01L 2225/06541 Conductive via connections through the device, e.g. vertical interconnects, through silicon via [TSV]
• CPC Class Codes: H01L 2225/06589 Thermal management, e.g. cooling
• CPC Class Codes: H01L 23/04 characterised by the shape of the container or parts, e.g. caps, walls
• CPC Class Codes: H01L 23/367 Cooling facilitated by shape of device H01L23/38, H01L23/40, H01L23/42, H01L23/44, H01L23/46 take precedence
• CPC Class Codes: H01L 23/42 Fillings or auxiliary members in containers or encapsulations selected or arranged to facilitate heating or cooling
• CPC Class Codes: H01L 23/49816 Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
• CPC Class Codes: H01L 25/0657 Stacked arrangements of devices
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/15311 being a ball array, e.g. BGA

Abstract

A semiconductor package includes a heat spreader. The semiconductor package includes a substrate, a first semiconductor chip disposed on the substrate, and a second semiconductor chip disposed on the first semiconductor chip. The heat spreader may be formed on the first semiconductor chip. A thermal interfacial material (TIM) layer may be formed to be in contact with the first semiconductor chip and the heat spreader and may cover side surfaces of the second semiconductor chip. Heat generated by the first semiconductor chip may be emitted through the TIM layer and the heat spreader. Thermal stress caused by a difference in coefficients of thermal expansion (CTEs) between the substrate and the first semiconductor chip may be distributed to ensure structural stability.

Claims

1. A semiconductor package comprising:

a substrate;

a first semiconductor chip disposed on the substrate;

a second semiconductor chip disposed on the first semiconductor chip;

a heat spreader disposed above the first semiconductor chip; and

a thermal interfacial material (TIM) layer being in contact with the first semiconductor chip and the heat spreader, the TIM layer further covering one or more side surfaces of the second semiconductor chip.

2. The package of claim 1, wherein the second semiconductor chip comprises a first side surface and a second side surface,

wherein the TIM layer is in contact with both the first and second side surfaces of the second semiconductor chip.

3. The package of claim 1, wherein the TIM layer is formed between a top surface of the second semiconductor chip and the heat spreader.

4. The package of claim 1, wherein the TIM layer is in contact with a side surface of the first semiconductor chip.

5. The package of claim 1, wherein a bottom surface of the heat spreader is arranged at a level that is lower than a bottom surface of the second semiconductor chip.

6. The package of claim 1, wherein a distance between a bottom surface of the heat spreader and a top surface of the first semiconductor chip is smaller than a distance between the second semiconductor chip and the first semiconductor chip.

7. The package of claim 1, wherein a side surface of the first semiconductor chip is exposed to an outside of the semiconductor package.

8. The package of claim 1, wherein the first semiconductor chip includes through-silicon vias (TSVs) formed through the first semiconductor chip.

9. The package of claim 1, further comprising:

an underfill disposed between the substrate and the first semiconductor chip;

an under-bump metallurgy (UBM) disposed on the TSVs; and

bumps formed through the underfill and connected to the UBM and the substrate.

10. A semiconductor package comprising:

a first semiconductor chip;

a second semiconductor chip arranged on the first semiconductor chip; and

a heat spreader arranged above the first semiconductor chip and configured to cover top and side surfaces of the second semiconductor chip,

wherein a bottom surface of the heat spreader is arranged at a level lower than a bottom surface of the second semiconductor chip.

11. The package of claim 10, wherein the bottom surface of the heat spreader is in thermal communication with the first semiconductor chip.

12. The package of claim 10, wherein a distance between the bottom surface of the heat spreader and a top surface of the first semiconductor chip is smaller than a distance between the second semiconductor chip and the first semiconductor chip.

13. The package of claim 10, wherein the heat spreader has a greater width than the first semiconductor chip.

14. The package of claim 10, wherein side surfaces of the first semiconductor chip are exposed to an outside of the semiconductor package.

15. The package of claim 10, further comprising a thermal interfacial material (TIM) layer disposed between the heat spreader and a top surface of the first semiconductor chip.

16. A semiconductor package comprising:

a substrate;

a first semiconductor chip arranged on the substrate;

a second semiconductor chip arranged on the first semiconductor chip;

a heat spreader covering a top and side surfaces of the second semiconductor chip; and

a thermal interface material (TIM) arranged between the heat spreader and the second semiconductor chip.

17. The package of claim 16, wherein the TIM is further arranged between an edge portion of the first semiconductor chip and the heat spreader.

18. The package of claim 16, further comprising an underfill arranged between the first semiconductor chip and the substrate, said underfill having a middle coefficient of thermal expansion (CTE) between that of the first semiconductor chip and the substrate.

19. The package of claim 16, further comprising one or more additional semiconductor chips arranged above the second semiconductor chip, wherein the heat spreader is configured to cover the second and one or more additional semiconductor chips.

20. The package of claim 16, wherein the heat spreader is configured having a porous or lattice-type structure to help dissipate heat from the heat spreader.