High-Voltage-Tolerant Pull-Up Resistor Circuit

• US 20150137881A1
• Filed: 11/19/2014
• Published: 05/21/2015
• Est. Priority Date: 11/19/2013
• Status: Active Grant

• Current Assignee: Semiconductor Manufacturing International (Shanghai) Corporation (Semiconductor Manufacturing International Corporation)
• Original Assignee: Semiconductor Manufacturing International (Shanghai) Corporation (Semiconductor Manufacturing International Corporation)
• Inventors: CHEN, JIE, WENG, WENJUN, ZHU, KAI, MO, SHANYUE, GUO, ZHIGUANG
• Granted Patent: US 9,634,662 B2
• Time in Patent Office: Days
• US Class Current: 327/543
• CPC Class Codes: H03K 19/00315 in field-effect transistor circuits
• CPC Class Codes: H03K 19/018507 Interface arrangements

Abstract

A pull-up resistor circuit is provided for an IC, including a voltage source, a voltage output for providing a first voltage to supply power for providing a second voltage for an input/output (I/O) port of the IC, a first PMOS transistor, a second PMOS transistor and a control signal generator. The first PMOS transistor and the second PMOS transistor are connected in series to provide pull-up resistance, where the first PMOS transistor is coupled to a first control signal to control a pull-up function of the pull-up resistor circuit in a normal mode. Further, the control signal generator is for generating a second control signal coupled to the second PMOS transistor to control a bias voltage of the pull-up resistor circuit to prevent a reverse current from the voltage output to the voltage source under a high-voltage-tolerant mode when the second voltage is higher than the first voltage.

Claims

1. A pull-up resistor circuit for an IC, comprising:

a voltage source for providing a first voltage to supply power;

a voltage output for providing a second voltage for an input/output (I/O) port of the IC;

a first PMOS transistor and a second PMOS transistor connected in serial to provide pull-up resistance, wherein the first PMOS transistor is coupled to a first control signal to control a pull-up function of the pull-up resistor circuit in a normal mode when the first voltage is higher than the second voltage; and

a control signal generator for generating a second control signal coupled to the second PMOS transistor to control a bias voltage of the pull-up resistor circuit to prevent a reverse current from the voltage output to the voltage source under a high-voltage-tolerant mode when the second voltage is higher than the first voltage.

2. The pull-up resistor circuit according to claim 1, wherein:

the first control signal is inputted on a gate of the first PMOS transistor;

a source of the first PMOS transistor is connected to the voltage source;

a drain of the first PMOS transistor is connected to a source of the second PMOS transistor, and a substrate of the first PMOS transistor is connected to a substrate of the second PMOS transistor and applied with the bias voltage, wherein a value of the bias voltage equals to a higher of the first voltage and the second voltage.

3. The pull-up resistor circuit according to claim 2, wherein:

the second control signal is applied on a gate of the second PMOS transistor, and a drain of the second PMOS transistor is connected to the voltage output; and

when the first voltage is higher than or equal to the second voltage and the first control signal is low, the second control signal is low, and when the first voltage is lower than the second voltage, the second control signal is at a same level of the second voltage.

4. The pull-up resistor circuit according to claim 3, wherein:

the control signal generator includes a first switch unit and a second switch unit.

5. The pull-up resistor circuit according to claim 4, wherein:

the first switch unit is connected between the gate of the second PMOS transistor and the voltage output;

the second switch unit is connected between the gate of the second PMOS transistor and ground; and

a turned-on impedance of the first switch unit is greater than a turned-on impedance of the second switch unit.

6. The pull-up resistor circuit according to claim 5, wherein:

when the first voltage is higher than or equal to the second voltage and the first control signal is low, the first switch unit is turned off;

when the first voltage is lower than the second voltage, the first switch unit is turned on; and

when the first voltage is higher than or equal to the second voltage and the first control signal is low, the second switch unit is turned on.

7. The pull-up resistor circuit according to claim 6, wherein:

the first switch unit including a third PMOS transistor;

a gate of the third PMOS transistor is connected to the voltage source;

a source of the third PMOS transistor is connected to the gate of the second PMOS transistor;

a drain of the third PMOS transistor is connected to the voltage output; and

a substrate of the third PMOS transistor is applied with the bias voltage.

8. The pull-up resistor circuit according to claim 7, wherein:

the impedance of the first switch unit is on is related to a width-to-length ratio of the third PMOS transistor.

9. The pull-up resistor circuit according to claim 7, wherein:

the second switch unit includes a fourth PMOS transistor and a first NMOS transistor;

a gate of the fourth PMOS transistor is connected to a drain of the fourth PMOS transistor and a drain of the first NMOS transistor;

a source of the fourth PMOS transistor is connected to the gate of the second PMOS transistor;

a substrate of the fourth PMOS transistor is used to apply the bias voltage;

a gate of the first NMOS transistor is inputted with a third control signal, wherein a signal level of the third control signal is opposite to a signal level of the first control signal; and

a source of the first NMOS transistor and a substrate of the first NMOS transistor are connected to ground.

10. The pull-up resistor circuit according to claim 7, wherein:

the second switch unit comprises a second NMOS transistor and a third NMOS transistor;

a gate of the second NMOS transistor is connected to the voltage source;

a drain of the second NMOS transistor is connected to the gate of the second PMOS transistor;

a source of the second NMOS transistor is connected to a drain of the third NMOS transistor;

a substrate of the second NMOS transistor is connected to a substrate of the third NMOS transistor and to ground;

a gate of the third NMOS transistor is inputted with a third control signal, wherein a signal level of the third control signal is opposite to a signal level of the first control signal; and

a source of the third NMOS transistor is connected to ground.

11. The pull-up resistor circuit according to claim 7, wherein:

the control signal generator comprises a third PMOS transistor, a fourth PMOS transistor, and a first NMOS transistor;

a gate of the third PMOS transistor is connected to the voltage source;

a source of the third PMOS transistor is connected to the gate of the second PMOS transistor;

a drain of the third PMOS transistor is connected to the voltage output;

a substrate of the third PMOS transistor is connected to a substrate of the fourth PMOS transistor and applied with the bias voltage;

a gate of the fourth PMOS transistor is connected to a drain of the fourth PMOS transistor and a drain of the first NMOS transistor;

a source of the fourth PMOS transistor is connected to the gate of the second PMOS transistor;

a gate of the first NMOS transistor is inputted with a third control signal, wherein a signal level of the third control signal is opposite to a signal level of the first control signal; and

a source of the first NMOS transistor is connected to a substrate of the first NMOS transistor and to ground.

12. The pull-up resistor circuit according to claim 3, wherein:

the control signal generator comprises a third PMOS transistor, a second NMOS transistor, and a third NMOS transistor;

a gate of the third PMOS transistor is connected to the voltage source;

a source of the third PMOS transistor is connected to the gate of the second PMOS transistor;

a drain of the third PMOS transistor is connected to the voltage output;

a substrate of the third PMOS transistor is applied with the bias voltage a gate of the second NMOS transistor is connected to the voltage source;

a drain of the second NMOS transistor is connected to the gate of the second PMOS transistor;

a substrate of the second NMOS transistor is connected to a substrate of the third NMOS transistor and to ground;

a gate of the third NMOS transistor is inputted with a third control signal, wherein a signal level of the third control signal is opposite to a signal level of the first control signal; and

a source of the third NMOS transistor is connected to ground.

13. The pull-up resistor circuit according to claim 1, further including a bias voltage generation circuit comprising a fifth PMOS transistor and a sixth PMOS transistor, wherein:

a gate of the fifth PMOS transistor is connected to a drain of the sixth PMOS transistor and to the voltage output;

a source of the fifth PMOS transistor is connected to a gate of the sixth PMOS transistor and to the voltage source;

a drain of the fifth PMOS transistor is connected to a source of the sixth PMOS transistor; and

a substrate of the fifth PMOS transistor is connected to a substrate of the sixth PMOS transistor and applied with the bias voltage.