SYSTEM, METHOD, AND COMPUTER PROGRAM PRODUCT FOR IMPLEMENTING ANTI-ALIASING OPERATIONS USING A PROGRAMMABLE SAMPLE PATTERN TABLE

• US 20150138228A1
• Filed: 11/15/2013
• Published: 05/21/2015
• Est. Priority Date: 11/15/2013
• Status: Active Grant

• Current Assignee: NVIDIA Corporation
• Original Assignee: NVIDIA Corporation
• Inventors: Lum, Eric B., Bolz, Jeffrey Alan, Bastos, Rui Manuel, Rodgers, Barry Nolan, Luiz, Gerald F., Lottes, Timothy Paul
• Granted Patent: US 9,437,040 B2
• Time in Patent Office: Days
• US Class Current: 345/611
• CPC Class Codes: G06T 15/005 General purpose rendering architectures
• CPC Class Codes: G06T 15/04 Texture mapping
• CPC Class Codes: G06T 15/405 using Z-buffer
• CPC Class Codes: G06T 15/503 Blending, e.g. for anti-aliasing
• CPC Class Codes: G06T 2200/12 involving antialiasing

Abstract

A system, method, and computer program product are provided for implementing anti-aliasing operations using a programmable sample pattern table. The method includes the steps of receiving an instruction that causes one or more values to be stored in one or more corresponding entries of the programmable sample pattern table and performing an anti-aliasing operation based on at least one value stored in the programmable sample pattern table. At least one value is selected from the programmable sample pattern table based on, at least in part, a location of one or more corresponding pixels.

Claims

1. A method comprising:

receiving an instruction that causes one or more values to be stored in one or more corresponding entries of a programmable sample pattern table; and

performing an anti-aliasing operation based on at least one value stored in the programmable sample pattern table,

wherein the at least one value is selected from the programmable sample pattern table based on, at least in part, a location of one or more corresponding pixels.

2. The method of claim 1, wherein each value in the programmable sample pattern table represents a relative sample location within a pixel.

3. The method of claim 2, wherein each value comprises two 4-bit integers.

4. The method of claim 2, wherein a first portion of the value represents a horizontal offset from a corner of the pixel and a second portion of the value represents a vertical offset from the corner of the pixel.

5. The method of claim 1, wherein each value comprises single-precision, floating-point numbers.

6. The method of claim 1, further comprising:

receiving a second instruction that causes the one or more new values to be stored in the programmable sample pattern table; and

performing a second anti-aliasing operation based on at least one new value stored in the programmable sample pattern table.

7. The method of claim 6, wherein the programmable sample pattern table is included in a first hardware unit of a processor and the second programmable sample pattern table is included in a second hardware unit of the processor.

8. The method of claim 7, wherein the first hardware unit implements at least a portion of a first stage of a graphics processing pipeline and the second hardware unit implements at least a portion of a second stage of the graphics processing pipeline.

9. The method of claim 7, further comprising transmitting the instruction to the second hardware unit, wherein the second instruction causes the second hardware unit to store the one or more values in the second programmable sample pattern table.

10. The method of claim 1, wherein the anti-aliasing operation comprises computing a z-value for a geometric primitive at a sample location specified by the at least one value.

11. The method of claim 1, wherein the anti-aliasing operation comprises generating a color value by sampling a texture map based on at least one texture coordinate interpolated at a sample location specified by the at least one value.

12. The method of claim 1, wherein the anti-aliasing operation comprises determining whether a sample location intersects at least one of a triangle, a line, and a point.

13. The method of claim 1, wherein the anti-aliasing operation comprises culling a graphics primitive when the graphics primitive does not intersect at least one sample location specified by the at least one value stored in the programmable sample pattern table.

14. The method of claim 1, wherein the one or more values are stored in one or more corresponding entries of a programmable sample pattern table based on an offset of a window relative to an origin of a surface.

15. The method of claim 1, wherein the instruction includes a pointer to a copy of the one or more values in a memory.

16. A computer-readable storage medium storing instructions that, when executed by a processor, causes the processor to perform steps comprising:

storing one or more values in one or more corresponding entries of a programmable sample pattern table; and

performing an anti-aliasing operation based on at least one value stored in the programmable sample pattern table,

wherein the at least one value is selected from the programmable sample pattern table based on, at least in part, a location of one or more corresponding pixels.

17. A system comprising:

a hardware unit configured to;

store one or more values in one or more corresponding entries of a programmable sample pattern table, and

perform an anti-aliasing operation based on at least one value stored in the programmable sample pattern table,

wherein the at least one value is selected from the programmable sample pattern table based on, at least in part, a location of one or more corresponding pixels.

18. The system of claim 17, further comprising;

a second hardware unit configured to;

store the one or more values in one or more corresponding entries of a second programmable sample pattern table, and

perform a second anti-aliasing operation based on at least one value stored in the second programmable sample pattern table.

19. The system of claim 17, wherein the system comprises a parallel processing unit (PPU) that includes the hardware unit.

20. The system of claim 19, further comprising:

a host processor coupled to the PPU via a bus, wherein the host processor is configured to generate instructions that cause the hardware unit to store the one or more values in the programmable sample pattern table; and

a memory storing a copy of the one or more values.