SYSTEM AND METHOD FOR POWER CONVERSION

• US 20150138859A1
• Filed: 11/15/2013
• Published: 05/21/2015
• Est. Priority Date: 11/15/2013
• Status: Abandoned Application

• Current Assignee: General Electric Company
• Original Assignee: General Electric Company
• Inventors: Zhou, Rui, Garces, Luis Jose, Tao, Fengfeng, Todorovic, Maja Harfman, Stephens, Charles Michael, Wang, Lei
• Application Number:
  US14/080,800
• Publication Number:
  US 20150138859A1
• Time in Patent Office: Days
• US Class Current: 363/132
• CPC Class Codes: H02M 1/0043 Converters switched with a phase shift, i.e. interleaved non-isolated DC/DC converters H02M3/1586
• CPC Class Codes: H02M 1/123 Suppression of common mode voltage or current
• CPC Class Codes: H02M 7/493 the static converters being arranged for operation in parallel

Abstract

A power conversion system is presented. The power conversion system includes a power converter. The power converter includes at least two circuits, where each of the at least two circuits includes two or more phase legs, where each of the two or more phase legs includes at least two semiconductor switches. Also, the at least two circuits includes an interphase reactor configured to couple one of the two or more phase legs to at least one other phase leg in the two or more phase legs. Moreover, the power conversion system includes a controller configured to obtain a switching pattern for each of the at least two semiconductor switches of the at least two circuits and selectively switch each of the at least two semiconductor switches based on the obtained switching pattern to reduce a common mode signal in the power conversion system. Method for power conversion is also presented.

Claims

1. A power conversion system, comprising:

a power converter, comprising;

at least two circuits, wherein each of the at least two circuits comprises;

two or more phase legs, wherein each of the two or more phase legs comprises at least two semiconductor switches;

an interphase reactor configured to operatively couple one of the two or more phase legs to at least one other phase leg in the two or more phase legs;

a controller configured to;

obtain a switching pattern for each of the at least two semiconductor switches corresponding to the at least two circuits; and

selectively switch each of the at least two semiconductor switches based on the obtained switching pattern to reduce a common mode signal in the power conversion system.

2. The system of claim 1, wherein the at least two semiconductor switches in each of the two or more phase legs comprise an insulated gate bipolar transistor, a metal oxide semiconductor field effect transistor, a field effect transistor, an injection enhanced gate transistor, an integrated gate commutated thyristor, or combinations thereof.

3. The power converter of claim 1, wherein the at least two semiconductor switches in each of the two or more phase legs comprise a gallium arsenide based switch, a gallium nitride based switch, a silicon carbide based switch, or combinations thereof.

4. The system of claim 1, wherein the at least two semiconductor switches comprise a power diode, a parasitic body diode, a discrete diode, or combinations thereof.

5. The system of claim 1, further comprising at least one direct current source, at least one direct current link, a load, or combinations thereof.

6. The system of claim 5, wherein the at least one direct current source comprises a fuel cell, a photovoltaic panel, a battery, or combinations thereof.

7. The system of claim 5, wherein the load comprises a grid, an electrical motor, or a combination thereof.

8. The system of claim 5, wherein the controller is configured to obtain the switching pattern based on a load demand.

9. The system of claim 1, wherein the controller comprises a phase locked loop control circuit.

10. The system of claim 1, wherein the controller is configured to generate a desired output parameter based on the selective switching of the at least two semiconductor switches corresponding to each of the at least two circuits.

11. The system of claim 10, wherein the controller is further configured to regulate an amplitude of the output parameter, a phase of the output parameter, or a combination thereof.

12. The system of claim 10, wherein the output parameter comprises a voltage, a current, or a combination thereof.

13. The system of claim 10, wherein the output parameter comprises a three-level voltage.

14. The system of claim 10, further comprising a filter configured to minimize ripple in the output parameter.

15. The system of claim 1, wherein the interphase reactor is configured to control a current circulating between the two or more phase legs in each of the at least two circuits.

16. A method for power conversion, comprising:

coupling at least two circuits, wherein the at least two circuits comprise two or more phase legs operatively coupled via an interphase reactor, wherein each of the two or more phase legs comprises at least two semiconductor switches;

obtaining a switching pattern for each of the at least two semiconductor switches in each of the two or more phase legs using a controller; and

selectively switching each of the at least two semiconductor switches in each of the two or more phase legs based on the obtained switching pattern to reduce a common mode signal in a power conversion system.

17. The method of claim 16, further comprising generating a desired output parameter based on the selective switching of each of the at least two semiconductor switches in each of the two or more phase legs.

18. The method of claim 17, further comprising regulating an amplitude of the output parameter, a phase of the output parameter, or a combination thereof.

19. The method of claim 16, wherein selectively switching each of the at least two semiconductor switches comprises activating and deactivating each of the at least two semiconductor switches corresponding to each of the two or more phase legs at similar frequencies.

20. The method of claim 16, wherein selectively switching each of the at least two semiconductor switches comprises activating and deactivating each of the at least two semiconductor switches corresponding to each of the two or more phase legs at phase-shifted frequencies.

21. The method of claim 16, wherein obtaining the switching pattern comprises using an interleaved bipolar pulse width modulation technique.