THREE-DIMENSIONAL SEMICONDUCTOR DEVICES AND FABRICATING METHODS THEREOF

• US 20150138862A1
• Filed: 10/27/2014
• Published: 05/21/2015
• Est. Priority Date: 11/15/2013
• Status: Active Grant

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Jae-Duk Lee, Jintaek Park, Youngwoo Park
• Inventors: PARK, JINTAEK, PARK, YOUNGWOO, LEE, JAEDUK
• Granted Patent: US 9,601,204 B2
• Time in Patent Office: Days
• US Class Current: 365/51
• CPC Class Codes: G11C 16/0466 comprising cells with charge storage in an insulating layer, e.g. metal-nitride-oxide-silicon [MNOS], silicon-oxide-nitride-oxide-silicon [SONOS] G11C16/0483, G11C16/0491 take precedence
• CPC Class Codes: G11C 16/0483 comprising cells having several storage transistors connected in series
• CPC Class Codes: G11C 16/10 Programming or data input circuits
• CPC Class Codes: G11C 5/02 Disposition of storage elements, e.g. in the form of a matrix array
• CPC Class Codes: G11C 5/025 Geometric lay-out considerations of storage- and peripheral-blocks in a semiconductor storage device geometrical lay-out of the components in integrated circuits, H01L27/0207
• CPC Class Codes: H01L 27/0688 Integrated circuits having a three-dimensional layout
• CPC Class Codes: H01L 27/092 complementary MIS field-effect transistors
• CPC Class Codes: H10B 43/27 the channels comprising vertical portions, e.g. U-shaped channels
• CPC Class Codes: H10B 43/35 with cell select transistors, e.g. NAND
• CPC Class Codes: H10B 43/40 characterised by the peripheral circuit region
• CPC Class Codes: H10B 43/50 characterised by the boundary region between the core and peripheral circuit regions

Abstract

A three-dimensional (3D) semiconductor memory device includes a CMOS circuit structure including a plurality of column blocks each comprising a plurality of page buffer circuits, and a lower wiring structure and a memory structure sequentially stacked over the CMOS circuit structure. The memory structure overlaps a first circuit region of the CMOS circuit structure and does not overlap a second circuit region of the CMOS circuit structure, and the plurality of column blocks are contained within the first circuit region of the CMOS circuit structure.

Claims

1. A three-dimensional (3D) semiconductor memory device, comprising:

a CMOS circuit structure including a plurality of column blocks each comprising a plurality of page buffer circuits; and

a lower wiring structure and a memory structure sequentially stacked over the CMOS circuit structure,

wherein the memory structure overlaps a first circuit region of the CMOS circuit structure and does not overlap a second circuit region of the CMOS circuit structure, and

wherein the plurality of column blocks are contained within the first circuit region of the CMOS circuit structure.

2. The device of claim 1, wherein the column blocks extend parallel to each other within the first region of the CMOS circuit structure.

3. The device of claim 2, wherein each of the column blocks further comprises a plurality of column selection circuits.

4. The device of claim 3, wherein page buffer circuits are contained within a page buffer block of each column block, and the column selection circuits are contained within a column selection block of each column block, and wherein the page buffer block extends parallel to the column selection block within each column block.

5. The device of claim 3, wherein each of the column blocks further comprises at least one of a control logic block and a voltage generator block.

6. The device of claim 1, wherein the memory structure comprises a plurality of memory blocks, and wherein each the column blocks is aligned below at least one of the memory blocks, respectively.

7. The device of claim 6, wherein the lower wiring structure includes a plurality of bit line structures located between a respective column block and the at least one of the memory blocks, and each of the bit line structures is connected to the respective column block and to the at least one of the memory blocks.

8. The device of claim 7, wherein the lower wiring structure further comprises input/ouput (I/O) line structures connecting the column blocks to each other.

9. The device of claim 8, wherein the CMOS circuit structure is located at a substrate surface that extends horizontally, and the bit line structures and the I/O line structures extend horizontally between the memory structure and the CMOS structure.

10. The device of claim 6, wherein each of the bit line structures is connected to a page buffer circuit in a corresponding one of the column blocks of the CMOS circuit structure, and the column blocks extend in a direction parallel to the bit line structures.

11. The device of claim 1, further comprising a row selection block contained within the second region of the CMOS circuit structure.

12. The device of claim 11, further comprising at least one of a control logic and a voltage generation block contained within the second region of the CMOS circuit structure.

13. A three-dimensional (3D) semiconductor memory device, comprising:

a substrate;

CMOS circuits located at a horizontal surface of the substrate;

a plurality of bit line structures connected to the CMOS circuits and extending horizontally over the CMOS circuits; and

a 3D memory cell array including a two-dimensional array of vertical structures over the bit line structures, each of the vertical structures including a plurality of memory cells,

wherein each of the bit line structures is further connected to a plurality of the vertical structures of the 3D memory cell array.

14. The device of claim 13, further comprising an input/output (I/O) line structure connected to the CMOS circuits and extending horizontally between the CMOS circuits and the bit lines structures.

15. The device of claim 14, wherein the I/O line structure extends in a same direction as the bit line structures.

16. The device of claim 14, wherein a cross-sectional area of the I/O line structure is greater than a cross-sectional area of each of the bit line structures.

17. The device of claim 13, wherein the bit lines structures are aligned below and connected to respective rows of vertical structures among the array of vertical structures.

18. The device of claim 13, further comprising an upper wiring layer located over the 3D memory cell array and electrically connected to the bit line structures through the vertical structures.

19. The device of claim 13, wherein each of the memory cells is a charge trap flash memory cell.

20. A three-dimensional (3D) semiconductor memory device, comprising:

a CMOS circuit structure; and

a lower wiring structure and a memory structure sequentially stacked over the CMOS circuit structure,

wherein the memory structure comprises first and second 3D memory array tiles located over the CMOS circuit structure, each of the 3D memory array tiles comprising memory cells arranged three-dimensionally,

the CMOS structure comprises a plurality of column blocks located below each of the first and second memory array tiles, and

the lower wiring structure comprises a plurality of bit line structures connected to the plurality of column blocks, respectively.

21. The device of claim 20, wherein each of the column blocks comprises at least one page buffer block and at least one column selection block.

22. The device of claim 20, wherein each of the 3D memory array tiles comprises a plurality of memory blocks, and the column blocks are aligned below at least one of the memory blocks, respectively.

23. The device of claim 20, wherein the column blocks and the bit line structures extend in a direction parallel to each other below a corresponding one of the first and second memory array tiles.

24. The device of claim 20, wherein each of the bit line structures is electrically connected to a page buffer circuit in a corresponding one of the plurality of column blocks and is electrically separated from others of the plurality of column blocks.

25. The device of claim 20, wherein at least one of the plurality of column blocks further comprises at least one of a control logic and a voltage generation circuit.

26. The device of claim 20, further comprising an I/O structure for electrically connecting the CMOS structure to an external electronic device,

wherein the lower wiring structure further comprises I/O line structures which electrically connect the column blocks to the I/O structure.

27. The device of claim 26, wherein the I/O line structures extend horizontally between the bit line structures and the CMOS structure.

28. The device of claim 20, wherein an electrical resistance of each of the bit line structures is greater than an electrical resistance of each of the I/O line structures.

29. The device of claim 28, wherein a cross-sectional area of each of the I/O line structures is larger than a cross-sectional area of each of the bit line structures.

30. The device of claim 20, further comprising an upper semiconductor pattern located over the memory structure,

wherein the memory structure comprises a two-dimensional array of vertical patterns,

each of the bit line structures is commonly connected to a respective row of vertical patterns among the array of vertical patterns, and

the upper semiconductor pattern is commonly connected to the array of vertical patterns, wherein the upper semiconductor pattern is electrically connected to the bit line structures through the vertical patterns.

31. A method of fabricating of a three-dimensional (3D) semiconductor memory device, comprising:

forming a CMOS structure on a substrate, the CMOS structure including a plurality column blocks arranged in respective rows,

forming a lower wiring structure including bit line structures on the CMOS structure, the bit line structures extending parallel to the rows of column blocks;

forming a memory structure on the lower wiring structure, the memory structure aligned over the CMOS structure and including a two-dimensional array of vertical patterns each extending vertically relative to the substrate; and

forming an upper wiring structure including an upper semiconductor pattern on the memory structure, the upper semiconductor pattern being connected to the bit line structures through the vertical patterns.

32. The method of claim 31, wherein the forming of the lower wiring structure further comprises forming input/output (I/O) line structures connecting the column blocks to each other, before the forming of the bit line structures.

33. The method of claim 31, wherein the lower wiring structure is formed of materials exhibiting heat-resistant properties at a maximum temperature utilized in the forming of the memory structure.