NONVOLATILE MEMORY DEVICES, OPERATING METHODS THEREOF AND MEMORY SYSTEMS INCLUDING THE SAME
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Abstract
Nonvolatile memory device, operating methods thereof, and memory systems including the same. In the operating method, a ground select line of a first string connected to a bit line may be floated. An erase prohibition voltage may be applied to a ground select line of a second string connected to the bit line. An erase operation voltage may be applied to the first and second strings.
13 Citations
36 Claims
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1-20. -20. (canceled)
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21. An operating method of a nonvolatile memory device including at least first through fourth strings on a substrate, each string including a plurality of memory cells and at least one select transistor sequentially stacked on the substrate in a direction perpendicular to the substrate, the operating method comprising:
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erasing first memory cells of a first portion of the first through fourth strings and preventing erasures of second memory cells of a second portion of the first through fourth strings, select transistors of the first and second strings being connected to a first select line, select transistors of the third and fourth strings being connected to a second select line, select transistors of the first and third strings being connected to a first bit line, and select transistors of the second and fourth strings being connected to a second bit line. - View Dependent Claims (22, 23, 24, 25, 26, 27, 28, 34, 35, 36)
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29. A storage device comprising:
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a nonvolatile memory including at least first through fourth strings on a substrate, each string including a plurality of memory cells and at least one select transistor sequentially stacked on the substrate in a direction perpendicular to the substrate, select transistors of the first and second strings being connected to a first select line, select transistors of the third and fourth strings being connected to a second select line, select transistors of the first and third strings being connected to a first bit line, and select transistors of the second and fourth strings being connected to a second bit line; and a memory controller configured to issue a control signal requesting an erase operation to the nonvolatile memory, the nonvolatile memory being configured to erase first memory cells of a first portion of the first through fourth strings and prevent erasures of second memory cells of a second portion of the first through fourth strings during the erase operation in response to the control signal requesting the erase operation. - View Dependent Claims (30, 31, 32, 33)
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Specification