SELF-HEALING DATA TRANSMISSION SYSTEM AND METHOD TO ACHIEVE DETERMINISTIC AND LOWER LATENCY

• US 20150139636A1
• Filed: 01/30/2015
• Published: 05/21/2015
• Est. Priority Date: 09/13/2013
• Status: Abandoned Application

• Current Assignee: Anova Technologies- SMG Holdings, LLC
• Original Assignee: Anova Technologies- SMG Holdings, LLC
• Inventors: Wisehart, Daniel J.
• Application Number:
  US14/610,118
• Publication Number:
  US 20150139636A1
• Time in Patent Office: Days
• US Class Current: 398/5
• CPC Class Codes: H04L 1/0061 Error detection codes
• CPC Class Codes: H04L 45/24 Multipath
• CPC Class Codes: H04L 45/44 Distributed routing
• CPC Class Codes: H04L 47/34 ensuring sequence integrity, e.g. using sequence numbers
• CPC Class Codes: H04L 49/552 by ensuring the integrity of packets received through redundant connections
• CPC Class Codes: H04Q 2011/0081 Fault tolerance; Redundancy; Recovery; Reconfigurability
• CPC Class Codes: H04Q 2011/0084 Quality of service aspects
• CPC Class Codes: H04W 24/04 Arrangements for maintaining operational condition

Abstract

The invention provides a method of simulcasting data fragments sent over a first packet-switched computer network to a trunk network and redistributed over a second packet-switched computer network. A method is provided comprising the steps of providing a trunk network including multiple links including an RF link and a fiber link, wherein all the transmission links transmit data packets to a receiver which will redistribute the earliest data packets with a matching frame check sequence (FCS) over the second packet switched computer network. The method provides for a sender for adding an incremental sender sequence number and sender FCS to the data packets, creating a sender data packet. Transmitting a sender data packet, simulcast over the transmission links, receiving, by a receiver, via the fastest links which may drop or change some bits unintentionally, a sender data packet and receiving, by the receiver, via slower links which are unlikely to drop or change some bits unintentionally, a sender data packet. The method provides for checking, by the receiver, a receiver calculated FCS of the received sender data packet and comparing them to the sender FCS that was added by the sender. Transmitting over the second packet-switched computer network, the first sender data packet with the next sequence number increment after the incremental sender sequence number and verifying sender FCS, verifying, by the receiver, the sender data packets and identifying, by the receiver, a gap between sender data packets, queueing up verified sender data packets when there is a gap in the verified sender data packets and sending all verified sender data packets in sequence order, once the gap is filled by any transmission link.

Claims

1. A logic device providing for low latency transmissions comprising:

a logic device having logic blocks providing a sender for simulcasting data packets to an RF link and a fiber link;

the sender undergoing a frame check sequence (FCS) to provide a sequence number for the data packets, the sender capable of determining good data packets; and

the logic device having a port to transmit data packets to the RF link and the fiber link in order to provide a self-healing function for reliably connecting two packet switched computer networks.

2. The logic device of claim 1 further comprising at least one 10G transceiver for transmitting data packets to the fiber link and the RF link.

3. The logic device of claim 1, located in a first LAN and paired with a second logic device located in a second LAN;

the sender in the first LAN creating a sender sequence number and a sender FCS and the second logic device having a receiver for segmenting good and bad data packets between the received data packets when the sender sequence number does not match the sender FCS.

4. The logic device of claim 3, wherein the receiver transmits good data fragments in sequence to the FIFO register to be decrypted.

5. The logic device of claim 1, wherein the RF transmission includes bit level packet sharing and a point-to-point construction and a Quality of Service (QOS) protocol that is altered to provide an out of band traffic algorithm.

6. The logic device of claim 1, wherein a console collects statistics while the simulcast data packet transmissions are occurring, wherein the console monitors the sender and receiver and posting the transmission statistics, via the console, after receiving decrypted data from the FIFO register.

7. The logic device of claim 1, wherein a comparator tests the relay during run time, using the fiber link in order reconfigure the logic device and changing a map section of the logic device according to customer reconfiguration requests.

8. The logic device of claim 1, wherein a fail-over occurs in 100 nanoseconds or less and the data packet is simulcast at different transmission rates via the RF link and the fiber link.

9. The logic device of claim 1, wherein the relay provides a deterministic system for precision measurement of latency reduction based on an logic device clock cycle of 3.103 nanoseconds or less.

10. The logic device of claim 1, wherein the logic device is a field programmable grid array (FPGA) having configurable logic blocks (CLB) linked to an 10G transceiver for simulcasting data packets to the RF and fiber links.