CACHE CONTROL APPARATUS AND METHOD

• US 20150143045A1
• Filed: 04/15/2014
• Published: 05/21/2015
• Est. Priority Date: 11/20/2013
• Status: Abandoned Application

• Current Assignee: Electronics and Telecommunications Research Institute
• Original Assignee: Electronics and Telecommunications Research Institute
• Inventors: HAN, Jin Ho, KWON, Young Su, SHIN, Kyoung Seon
• Application Number:
  US14/253,466
• Publication Number:
  US 20150143045A1
• Time in Patent Office: Days
• US Class Current: 711/122
• CPC Class Codes: G06F 12/0862 with prefetch
• CPC Class Codes: G06F 12/0897 with two or more cache hierarchy levels with multilevel cache hierarchies G06F12/0811
• CPC Class Codes: G06F 2212/1021 Hit rate improvement
• CPC Class Codes: G06F 2212/6022 Using a prefetch buffer or dedicated prefetch cache

Abstract

Provided are a cache control apparatus and method for reducing a miss penalty. The cache control apparatus includes a first level cache configured to store data in a memory, a second level cache connected to the first level cache, and configured to be accessed by a processor when the first level cache fails to call data according to a data request instruction, a prefetch buffer connected to the first and second level caches, and configured to temporarily store data transferred from the first and second level caches to a core, and a write buffer connected to the first level cache, and configured to receive address information and data of the first level cache.

Claims

1. A cache control apparatus comprising:

a first level cache configured to store data in a memory;

a second level cache connected to the first level cache, and configured to be accessed by a processor when the first level cache fails to call data according to a data request instruction;

a prefetch buffer connected to the first and second level caches, and configured to temporarily store data transferred from the first and second level caches to a core; and

a write buffer connected to the first level cache, and configured to receive address information and data of the first level cache.

2. The cache control apparatus of claim 1, wherein the second level cache is a write-though cache, and forms an inclusive cache structure with the first level cache.

3. The cache control apparatus of claim 1, wherein the prefetch buffer receives and stores data of a data read operation of at least one of the first and second level caches.

4. The cache control apparatus of claim 3, wherein when the first level cache fails to call the data, the prefetch buffer reads information of a line including the data request instruction and a line continued therewith before accessing the second level cache, and stores information of the continued line.

5. The cache control apparatus of claim 4, wherein the first level cache calls requested data from the continued line according to the data request instruction.

6. The cache control apparatus of claim 1, wherein the write buffer receives and stores data of a data write operation of the first level cache.

7. The cache control apparatus of claim 6, wherein,

the write buffer comprises a plurality of buffers, and

when the data of the data write operation includes continuous address information, the write buffer stores the data of the data write operation in the plurality of buffers in consideration of the address information.

8. The cache control apparatus of claim 2, wherein the second level cache receives dirty information of the first level cache which is generated due to a data mismatch between a memory and the first level cache, performs a read operation on the received dirty information, and performs, by predetermined double words, the write operation on the dirty information.

9. The cache control apparatus of claim 2, wherein, in a flush operation of the first level cache, the first level cache transmits information about the flush operation of the first level cache to the second level cache.

10. The cache control apparatus of claim 9, wherein the write buffer receives and stores the information about the flush operation of the first level cache, and transmits the stored information about the flush operation to the memory.

11. A cache control method comprising:

receiving a data request instruction;

calling data for the first level cache according to the data request instruction;

when the first level cache fails to call the data, reading information of a line continued with a line including the data request instruction;

temporarily storing data, transferred from the first level cache or the second level cache to a core, in a prefetch buffer in a cache read operation; and

receiving address information and data of the first level cache in the cache read operation.

12. The cache control method of claim 11, further comprising writing dirty information of the first level cache in the second level cache.

13. The cache control method of claim 12, wherein the writing of dirty information comprises receiving the dirty information of the first level cache which is generated due to a data mismatch between a memory and the first level cache, and writing, by predetermined double words, the dirty information of the first level cache in the second level cache.

14. The cache control method of claim 12, further comprising, in a flush operation of the first level cache, transmitting information about the flush operation of the first level cache to the second level cache and a write buffer in consideration of the dirty information of the first level cache.

15. The cache control method of claim 11, wherein the reading of a line comprises, when the first level cache fails to call the data, reading the information of the line continued with the line including the data request instruction.

16. The cache control method of claim 11, wherein the receiving of address information and data comprises, when data of the cache write operation includes continuous address information, receiving the data of the cache write operation to store the received data in a plurality of buffers in consideration of the continuous address information.