Array Substrate For Display Device And Method Of Fabricating The Same

• US 20150144910A1
• Filed: 11/13/2014
• Published: 05/28/2015
• Est. Priority Date: 08/12/2013
• Status: Active Grant

• Current Assignee: LG Display Co., Ltd.
• Original Assignee: LG Display Co., Ltd.
• Inventors: Beak, Jung-Sun, Kim, Jeong-Oh, Kim, Yong-Min, Kim, Min-Joo, Yun, Jeong-Gi
• Granted Patent: US 9,093,330 B2
• Time in Patent Office: Days
• US Class Current: 257/40
• CPC Class Codes: H01L 27/1225 with semiconductor materials not belonging to the group IV of the periodic table, e.g. InGaZnO
• CPC Class Codes: H01L 27/124 with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits wiring structures per se H01L23/52
• CPC Class Codes: H01L 27/1255 integrated with passive devices, e.g. auxiliary capacitors
• CPC Class Codes: H10K 59/1216 the pixel elements being capacitors
• CPC Class Codes: H10K 59/123 Connection of the pixel electrodes to the thin film transistors [TFT]

Abstract

An array substrate for a display device includes a first thin film transistor (TFT) including a first semiconductor layer, a first gate electrode corresponding to the first semiconductor layer, a first source electrode and a first drain electrode; a second TFT including a second semiconductor layer, a second gate electrode corresponding to the second semiconductor layer, a second source electrode and a second drain electrode; a first transparent capacitor electrode connected to the first drain electrode; a first passivation layer on the first transparent capacitor electrode; a second transparent capacitor electrode on the first passivation layer and connected to the second drain electrode, the second transparent capacitor electrode overlapping the first transparent capacitor electrode; a second passivation layer on or over the first passivation layer and the second transparent capacitor electrode; and a first electrode on the second passivation layer and connected to the second transparent capacitor electrode.

Claims

1. An array substrate for a display device, comprising:

a first thin film transistor (TFT) including a first semiconductor layer, a first gate electrode corresponding to the first semiconductor layer, a first source electrode and a first drain electrode;

a second TFT including a second semiconductor layer, a second gate electrode corresponding to the second semiconductor layer, a second source electrode and a second drain electrode;

a first transparent capacitor electrode connected to the first drain electrode;

a first passivation layer on the first transparent capacitor electrode;

a second transparent capacitor electrode on the first passivation layer and connected to the second drain electrode, the second transparent capacitor electrode overlapping the first transparent capacitor electrode;

a second passivation layer on or over the second transparent capacitor electrode; and

a first electrode on the second passivation layer and connected to the second transparent capacitor electrode.

2. The array substrate according to claim 1, wherein the first drain electrode includes a transparent layer and a metal layer on the transparent layer, and the first capacitor electrode extends from the transparent layer.

3. The array substrate according to claim 2, wherein the transparent layer includes indium-tin-oxide.

4. The array substrate according to claim 2, wherein each of the first source electrode, the second source electrode and the second drain electrode includes the transparent layer and the metal layer.

5. The array substrate according to claim 1, further comprising a color filter between the first and second passivation layers.

6. The array substrate according to claim 1, further comprising an organic emitting layer on the first electrode and a second electrode on the organic emitting layer.

7. An array substrate for a display device, comprising:

a first thin film transistor (TFT) including a first semiconductor layer, a first gate electrode corresponding to the first semiconductor layer, a first source electrode and a first drain electrode;

a second TFT including a second semiconductor layer, a second gate electrode corresponding to the second semiconductor layer, a second source electrode and a second drain electrode;

a first transparent capacitor electrode connected to the first drain electrode or the second semiconductor layer;

an interlayer insulating layer on the first transparent capacitor electrode;

a second transparent capacitor electrode on the interlayer insulating layer and connected to the second drain electrode, the second transparent capacitor electrode overlapping the first transparent capacitor electrode;

a first passivation layer on or over the second transparent capacitor electrode; and

a first electrode on the first passivation layer and connected to the second drain electrode.

8. The array substrate according to claim 7, wherein the first transparent capacitor electrode is disposed at the same layer and includes the same material as the first and second semiconductor layers.

9. The array substrate according to claim 8, wherein the first transparent capacitor electrode includes an indium-gallium-zinc-oxide layer.

10. The array substrate according to claim 7, wherein the second drain electrode includes a transparent layer and a metal layer on the transparent layer, and the second capacitor electrode extends from the transparent layer.

11. The array substrate according to claim 10, wherein the transparent layer includes indium-tin-oxide.

12. The array substrate according to claim 10, wherein each of the first source electrode, the second source electrode and the second drain electrode includes the transparent layer and the metal layer.

13. The array substrate according to claim 7, further comprising:

a second passivation layer between the first passivation layer and the second transparent capacitor electrode; and

a color filter between the first and second passivation layers.

14. The array substrate according to claim 7, further comprising an organic emitting layer on the first electrode and a second electrode on the organic emitting layer.

15. An array substrate for a display device, comprising:

a first thin film transistor (TFT) including a first semiconductor layer, a first gate electrode corresponding to the first semiconductor layer, a first source electrode and a first drain electrode;

a second TFT including a second semiconductor layer, a second gate electrode corresponding to the second semiconductor layer, a second source electrode and a second drain electrode;

a first transparent capacitor electrode electrically coupled to at least one of the first drain electrode and the second semiconductor layer;

a first nonconductive layer on the first transparent capacitor electrode;

a second transparent capacitor electrode on the first nonconductive layer overlapping the first transparent capacitor electrode, the second transparent capacitor electrode electrically coupled to the second drain electrode;

a second nonconductive layer on or over at least the second transparent capacitor electrode; and

an anode electrode on the second nonconductive layer and electrically coupled to at least one of the second transparent capacitor electrode and the second drain electrode.

16. The array substrate according to claim 15, wherein an organic emitting layer overlaps the first and second transparent capacitor electrodes.

17. The array substrate according to claim 15, wherein the first nonconductive layer is a first passivation layer and the second nonconductive layer is a second passivation layer.

18. The array substrate according to claim 15, wherein the second nonconductive layer is also on or over the first passivation layer.

19. The array substrate according to claim 15, wherein the first nonconductive layer is an interlayer insulating layer and the second nonconductive layer is a first passivation layer.

20. The array substrate according to claim 15, wherein the second nonconductive layer is also on or over at least the first and second TFTs.