CMOS Devices with Reduced Leakage and Methods of Forming the Same

• US 20150145002A1
• Filed: 11/22/2013
• Published: 05/28/2015
• Est. Priority Date: 09/13/2013
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Lee, Yi-Jing, Wu, Cheng-Hsien, Ko, Chih-Hsin, Wann, Clement Hsingjen
• Granted Patent: US 9,224,734 B2
• Time in Patent Office: Days
• US Class Current: 257/192
• CPC Class Codes: H01L 21/02236 group IV semiconductor
• CPC Class Codes: H01L 21/02238 silicon in uncombined form, i.e. pure silicon
• CPC Class Codes: H01L 21/02255 formation by thermal treatment H01L21/02252 takes precedence; after treatment of an insulating film H01L21/3105 and subgroups
• CPC Class Codes: H01L 21/02532 Silicon, silicon germanium, germanium
• CPC Class Codes: H01L 21/0262 Reduction or decomposition of gaseous compounds, e.g. CVD
• CPC Class Codes: H01L 21/30604 Chemical etching
• CPC Class Codes: H01L 21/30608 Anisotropic liquid etching H01L21/3063 takes precedence
• CPC Class Codes: H01L 21/3065 Plasma etching; Reactive-ion etching
• CPC Class Codes: H01L 21/3085 characterised by their behaviour during the process, e.g. soluble masks, redeposited masks
• CPC Class Codes: H01L 21/31 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques encapsulating layers H01L21/56; After treatment of these layers; Selection of materials for these layers
• CPC Class Codes: H01L 21/32 using masks
• CPC Class Codes: H01L 21/76224 using trench refilling with dielectric materials trench filling with polycristalline silicon H01L21/763; together with vertical isolation, e.g. trench refilling in a SOI substrate H01L21/76264
• CPC Class Codes: H01L 21/823807 with a particular manufacturing method of the channel structures, e.g. channel implants, halo or pocket implants, or channel materials
• CPC Class Codes: H01L 21/823878 isolation region manufacturing related aspects, e.g. to avoid interaction of isolation region with adjacent structure
• CPC Class Codes: H01L 27/0922 Combination of complementary transistors having a different structure, e.g. stacked CMOS, high-voltage and low-voltage CMOS
• CPC Class Codes: H01L 29/0653 adjoining the input or output region of a field-effect device, e.g. the source or drain region
• CPC Class Codes: H01L 29/1054 with a variation of the composition, e.g. channel with strained layer for increasing the mobility
• CPC Class Codes: H01L 29/161 including two or more of the elements provided for in group H01L29/16 , e.g. alloys H01L29/1604 takes precedence
• CPC Class Codes: H01L 29/165 in different semiconductor regions , e.g. heterojunctions
• CPC Class Codes: H01L 29/66575 where the source and drain or source and drain extensions are self-aligned to the sides of the gate H01L29/66606 takes precedence

Abstract

A device includes a first semiconductor layer, and a second semiconductor layer over the first semiconductor layer. The first semiconductor layer and the second semiconductor layer comprise different materials. A semiconductor region is overlying and contacting the second semiconductor layer, wherein a bottom surface of the semiconductor region contacts a first top surface of the second semiconductor layer. The semiconductor region and the second semiconductor layer comprise different material. The bottom surface of the semiconductor region has a slanted portion contacting a (551) surface plane of the second semiconductor layer.

Claims

1. A device comprising:

a first semiconductor layer;

a second semiconductor layer over the first semiconductor layer, wherein the first semiconductor layer and the second semiconductor layer comprise different materials; and

a semiconductor region over and contacting the second semiconductor layer, wherein a bottom surface of the semiconductor region contacts a first top surface of the second semiconductor layer, wherein the semiconductor region and the second semiconductor layer comprise different materials, and wherein the bottom surface of the semiconductor region comprises a first slanted portion contacting a first (551) surface plane of the second semiconductor layer.

2. The device of claim 1, wherein the first semiconductor layer comprises a first silicon germanium having a first germanium percentage, the second semiconductor layer is a silicon layer, and the semiconductor region comprises a second silicon germanium having a second germanium percentage higher than the first germanium percentage.

3. The device of claim 1, wherein the bottom surface of the semiconductor region further comprises a second slanted portion contacting a second (551) surface plane of the second semiconductor layer.

4. The device of claim 3, wherein the first slanted portion joins the second slanted portion to form a V-Shape in a cross-sectional view of the device.

5. The device of claim 3, wherein the bottom surface of the semiconductor region further comprises flat portion, wherein the first slanted portion and the second slanted portion are connected to opposite ends of the flat portion, and wherein the flat portion is parallel to a major top surface of the first semiconductor layer.

6. The device of claim 1 further comprising:

a P-type Metal-Oxide-Semiconductor (PMOS) device comprising a portion of the semiconductor region as a first channel region;

a Shallow Trench Isolation (STI) region extending from a second top surface of the second semiconductor layer into the second semiconductor layer, with the second top surface of the second semiconductor layer is higher than the first top surface of the second semiconductor layer;

a N-type Metal-Oxide-Semiconductor (NMOS) device comprising;

a portion of the second semiconductor layer as a second channel region;

a gate stack over the second channel region; and

a source/drain region between the second channel region and the STI region, with the source/drain region in contact with an edge of the STI region; and

an oxide region in the first semiconductor layer, wherein the oxide region extends beyond the edge of the STI region, and comprises a portion overlapped by the source/drain region.

7. The device of claim 6, wherein the oxide region is un-overlapped by at least a portion of the second channel region.

8. The device of claim 6, wherein an entirety of the source/drain region and an entirety of the second channel region overlap the oxide region.

9. A device comprising:

a silicon substrate;

a silicon germanium layer having a first germanium percentage;

a silicon layer over the silicon germanium layer;

a silicon germanium region having a bottom surface over and contacting a first top surface of the silicon layer, wherein the silicon germanium region has a second germanium percentage higher than the first germanium percentage;

a P-type Metal-Oxide-Semiconductor (PMOS) device comprising;

a first gate dielectric over the silicon germanium region;

an N-type Metal-Oxide-Semiconductor (NMOS) device comprising;

a second gate dielectric over a second top surface of the silicon layer; and

a source/drain region adjacent to the second gate dielectric;

a first Shallow Trench Isolation (STI) region in the silicon layer, wherein the first STI region contacts the source/drain region; and

a first silicon germanium oxide region in the silicon germanium layer, the first silicon germanium oxide region comprising;

a first portion underlying and contacting the first STI region; and

a second portion overlapped by the source/drain region of the NMOS device.

10. The device of claim 9 further comprising:

an additional source/drain region comprised in the PMOS device, wherein the additional source/drain region is adjacent to the first gate dielectric, and wherein a portion of the silicon germanium region forms a portion of the additional source/drain region;

a second STI region in the silicon layer, wherein the second STI region contacts the additional source/drain region; and

a second silicon germanium oxide region in the silicon germanium layer, wherein an entirety of the second silicon germanium oxide region is not overlapped by the additional source/drain region.

11. The device of claim 9, wherein the bottom surface of the silicon germanium region comprises a first slanted portion contacting a first (551) surface plane of the silicon layer.

12. The device of claim 11, wherein the bottom surface of the silicon germanium region further comprises a second slanted portion contacting a second (551) surface plane of the silicon layer.

13. The device of claim 12, wherein the first slanted portion joins the second slanted portion to form a V-Shape in a cross-sectional view of the device.

14. The device of claim 12, wherein the first slanted portion and the second slanted portion are connected to opposite ends of a flat portion of the bottom surface of the silicon germanium region, and wherein the flat portion is parallel to a major top surface of the silicon substrate.

15. A method comprising:

performing a first epitaxy to form a silicon germanium layer over a substrate, wherein the silicon germanium layer has a first germanium percentage;

performing a second epitaxy to form a silicon layer over the silicon germanium layer;

etching the silicon layer to form a trench, with a bottom portion of silicon layer left under the trench, wherein the bottom portion of the silicon layer has a top surface comprising a first slanted portion, with the first slanted portion comprising a (551) plane of the silicon layer;

performing a third epitaxy to form a silicon germanium region in the trench, wherein the silicon germanium region has a bottom surface over and contacting the top surface of the silicon layer; and

forming a P-type Metal-Oxide-Semiconductor (PMOS) device comprising;

forming a first gate dielectric over a top surface of the silicon germanium region, with a channel region of the PMOS device in the silicon germanium region.

16. The method of claim 15, wherein after the etching the silicon layer, the top surface of the bottom portion of the silicon layer further comprises a second slanted portion at an additional (551) surface plane of the silicon layer.

17. The method of claim 16, wherein the first slanted portion joins the second slanted portion to form a V-Shape.

18. The method of claim 16, wherein the first slanted portion and the second slanted portion are connected to opposite ends of a flat portion of the top surface of the silicon layer, and wherein the flat portion is parallel to a major top surface of the substrate.

19. The method of claim 15 further comprising:

before the etching the silicon layer to form the trench, forming a first additional trench and a second additional trench in the silicon layer;

forming a mask layer to cover a bottom and sidewalls of the first additional trench, wherein a bottom and sidewalls of the second additional trench are not covered by the mask layer;

performing an oxidation on the silicon germanium layer through the second additional trench to form a silicon germanium oxide region in the silicon germanium layer; and

filling the first additional trench and the second additional trench to form a first Shallow Trench Isolation (STI) region and a second STI region, respectively; and

forming an N-type Metal-Oxide-Semiconductor (NMOS) device comprising;

forming a second gate dielectric over the silicon layer, with a portion of the silicon layer being a channel region of the NMOS device; and

forming a source/drain region adjacent to the second gate dielectric, wherein a portion of the source/drain region overlaps a portion of the silicon germanium oxide region.

20. The method of claim 19, wherein a channel region of the NMOS device overlaps the silicon germanium oxide region.