LOW POWER CONSUMPTION AC LOAD SWITCHES

• US 20150145347A1
• Filed: 11/22/2013
• Published: 05/28/2015
• Est. Priority Date: 11/22/2013
• Status: Active Grant

• Current Assignee: Ademco Inc. (Resideo Technologies, Inc.)
• Original Assignee: Honeywell International Inc.
• Inventors: Juntunen, Robert D., Kim, Hyunki
• Granted Patent: US 9,673,811 B2
• Time in Patent Office: Days
• US Class Current: 307/113
• CPC Class Codes: H03K 17/687 the devices being field-effect transistors
• CPC Class Codes: H03K 17/691 using transformer coupling
• CPC Class Codes: H03K 2217/0009 AC switches, i.e. delivering AC power to a load
• CPC Class Codes: H03K 2217/0036 Means reducing energy consumption
• CPC Class Codes: H03K 2217/0063 High side switches, i.e. the higher potential [DC] or life wire [AC] being directly connected to the switch and not via the load
• CPC Class Codes: H03K 2217/0072 Low side switches, i.e. the lower potential [DC] or neutral wire [AC] being directly connected to the switch and not via the load

Abstract

A circuit for ensuring ultra-low power relay switching to control an AC load and extend a battery'"'"'s lifetime. A control circuit may be designed to work where power is provides at very low duty cycle in that the on-time of applied voltage is quite short compared to its off-time. During the on-time, power such as that from a battery may be consumed to drive the circuit but overall such consumption of power is almost miniscule, for instance, a few microamperes or less from a three volt battery. An input FET may drive a pair switching FETs that provide pulses to a transformer which provides a ramp of voltage that remains above zero volts to a pair of AC switch FETs. An output of the AC switch may go to operate relays of a wire saver for operating one or more thermostats.

Claims

1. A mechanism for low power consumption load switches, comprising:

a switch having an input terminal for a low duty cycle signal having a duty cycle of less than ten percent, and having an output terminal for connection to a voltage supply;

a dual switch having a first input terminal connected to the output terminal of the single switch, a second input terminal connected to the input terminal of the single switch, and having first and second output terminals, respectively;

a transformer having a first end of a primary winding connected to the second output terminal of the dual switch, a second end of the primary winding connected to the first output terminal of the dual switch, and having a first end and a second end of a secondary winding; and

an AC switch having a first terminal connected to the first end of the secondary winding of the transformer, a second terminal connected to the second end of the secondary winding of the transformer, and having third and fourth terminals.

2. The mechanism of claim 1, wherein the third and fourth terminals of the AC switch are for connection to a load.

3. The mechanism of claim 1, wherein the low duty cycle signal comprises a series of pulses.

4. The mechanism of claim 2, wherein a signal appearing across the first and second ends of the primary winding of the transformer, starts at a trailing edge of each pulse of the low duty cycle signal, with an initial maximum magnitude and, within a period of time less than a width of a pulse of the low duty cycle signal, ramps down to zero.

5. The mechanism of claim 2, wherein a signal appearing at the first terminal of the AC switch starts at a leading edge of the signal appearing across the first and second ends of the primary winding of the transformer, then rises to a first voltage and then ramps down to a second voltage, where the signal at a next leading edge of the signal appearing across the first and second ends of the primary winding of the transformer, then rises to the first voltage and then ramps down to the second voltage at a next leading edge of a next signal appearing across the first and second ends of the primary winding of the transformer, in a repetitive manner as long as the low duty cycle signal appears at the input of the signal switch and the voltage supply is provided at the output terminal of the single switch.

6. The mechanism of claim 2, wherein an amount of current from the voltage supply ranges from one-tenth microampere to one milliampere for a control current at the load greater than ten milliamperes.

7. A method for low power switching of a load, comprising:

providing an input FET for receiving a low duty cycle signal having a duty cycle of less than ten percent and for connection to a supply voltage, to be switched in accordance with the low duty cycle signal;

connecting an input of a high side FET to an output of the input FET;

connecting an input of a low side FET to a terminal for receiving the low duty cycle signal;

connecting a first end of a primary winding of a transformer to an output of the low side FET;

connecting a second end of the primary winding of the transformer to an output of the high side FET;

connecting a first end of a secondary winding of the transformer to an input of a first AC switch FET and an input of a second AC switch FET;

connecting a second end of the secondary winding of the transformer to a first terminal of the first AC switch FET and a first terminal of the second AC switch FET; and

connecting a second terminal of the first AC switch FET and a second terminal of the second AC switch FET to an AC load.

8. The method of claim 7, wherein:

the input FET is an N-channel device;

the high side FET is a P-channel device;

the low side FET is an N-channel device;

the first AC switch FET is an N-channel device; and

the second AC switch FET is an N-channel device.

9. The method of claim 7, wherein:

the low duty cycle signal, comprising pluses, has a duty cycle less than five percent; and

a signal appearing across the first and second ends of the primary winding of the transformer, begins at a trailing edge of each pulse of the low duty cycle signal, with an initial maximum magnitude and after a period of time less than a period of time of a width of pulse of the low duty cycle signal, ramps with a decline to a minimum magnitude.

10. The method of claim 7, wherein a signal appearing on an input of the first AC switch FET starts at a leading edge of the signal appearing across the first and second ends of the primary winding of the transformer, rises to first voltage and then declines to a second voltage, where a next leading edge of a signal appearing across the first and second ends of the primary winding rises to the first voltage and then declines to the second voltage at a next signal appearing across the first and second ends of the primary winding, in a repetitive manner as long as the low duty cycle signal is being received by the input FET, and connection to the supply voltage is present at the input FET.

11. The method of claim 7, wherein an amount of current from the supply voltage ranges from one-tenth microampere to one milliampere for a control current of ten milliamperes or greater at the AC load.

12. A load switch system comprising:

an input interface;

a signal conditioner and driver connected to the input interface;

an inductive load connected to the signal conditioner and driver; and

an AC switch connected to the inductive load; and

wherein a signal to the input interface has a duty cycle less than ten percent.

13. The system of claim 12, wherein:

the input interface comprises a transistor having an input for receiving the signal;

the signal conditioner and driver comprise a dual channel circuit;

the inductive load comprises a transformer; and

the AC switch comprises a dual transistor AC switch.

14. The system of claim 13, wherein:

the dual channel circuit has a first input connected to an output of the transistor, and a second input connected to the input of the transistor;

the transformer has a first end of a primary winding connected to a first output of the dual channel circuit and a second end of the primary winding connected to a second output of the dual channel circuit; and

the dual transistor AC switch has a first common terminal connected to a first end of a secondary winding of the transformer, a second common terminal connected to a second end of the secondary winding of the transformer, and a first output and second output connected to an AC load.

15. The system of claim 14, wherein:

the input of the transistor is for the signal having a duty cycle;

the output of the transistor and the first input of the dual channel circuit are for connection via a resistor to a battery voltage;

a first common terminal of the dual channel circuit is for connection to a battery voltage; and

a common terminal of the transistor and a second common terminal of the dual channel circuit are for connection to a ground having a zero voltage reference.

16. The system of claim 13, wherein the duty cycle is less than one-tenth percent.

17. The system of claim 14, wherein:

the transistor comprises an N-channel FET;

the dual channel circuit comprises a P-channel FET and an N-channel FET; and

the dual transistor AC switch comprises a first N-channel FET and a second N-channel FET.

18. The system of claim 15, wherein:

the input of the transistor comprises a gate of a FET;

the output of the transistor comprises a drain of the FET;

the first input of the dual channel circuit comprises a gate of a first FET;

the first common terminal of the dual channel circuit comprises a source of the first FET;

the common terminal of the transistor comprises a source of the FET;

the second common terminal of the dual channel circuit comprises a source of a second FET;

the first output of the dual channel circuit comprises a drain of the first FET; and

the second output of the dual channel circuit comprises a drain of the second FET.

19. The system of claim 14, further comprising a diode connected in series between the second common terminal of the dual transistor AC switch and the second end of the secondary winding of the transformer.

20. The system of claim 14, wherein:

the second common terminal of the dual transistor AC switch comprises first and second gates of a first FET and a second FET, respectively, of the dual transistor AC switch; and

the first common terminal of the dual transistor AC switch comprises a first source and second source of the first FET and the second FET, respectively, of the dual transistor AC switch; and

the first output and the second output connected to the AC load comprise a first drain and second drain of the first FET and the second FET, respectively, of the dual transistor AC switch.