CANCELLATION OF DELTA-SIGMA QUANTIZATION NOISE WITHIN A FRACTIONAL-N PLL WITH A NONLINEAR TIME-TO-DIGITAL CONVERTER

• US 20150145571A1
• Filed: 07/31/2014
• Published: 05/28/2015
• Est. Priority Date: 11/27/2013
• Status: Active Grant

• Current Assignee: Skyworks Solutions Incorporated
• Original Assignee: Silicon Laboratories Incorporated
• Inventors: Perrott, Michael H.
• Granted Patent: US 9,490,818 B2
• Time in Patent Office: Days
• US Class Current: 327/159
• CPC Class Codes: G04F 10/005 Time-to-digital converters [TDC] analog-to-digital converters with intermediate conversion to time or phase H03M1/50, H03M1/60
• CPC Class Codes: H02M 3/07 using capacitors charged and discharged alternately by semiconductor devices with control electrode , e.g. charge pumps
• CPC Class Codes: H03L 7/0802 the loop being adapted for reducing power consumption H03L7/14 takes precedence
• CPC Class Codes: H03L 7/085 concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal H03L7/10 takes precedence; circuits for comparing the phase or frequency of two mutually-independent oscillations H03D13/00
• CPC Class Codes: H03L 7/093 using special filtering or amplification characteristics in the loop H03L7/087 - H03L7/091 take precedence
• CPC Class Codes: H03L 7/0995 the oscillator comprising a ring oscillator
• CPC Class Codes: H03M 1/0836 of phase error, e.g. jitter
• CPC Class Codes: H03M 1/0854 of quantisation noise
• CPC Class Codes: H03M 1/66 Digital/analogue converters H03M1/001 – H03M1/10 take precedence
• CPC Class Codes: H03M 3/358 of non-linear distortion, e.g. instability avoiding instability by structural design H03M3/44
• CPC Class Codes: H03M 3/368 of noise other than the quantisation noise already being shaped inherently by delta-sigma modulators
• CPC Class Codes: H03M 7/3004 Digital delta-sigma modulation

Abstract

A fractional-N phase-locked loop (PLL) includes a nonlinear time to digital converter that generates a digital representation of a phase error corresponding to a time difference between a feedback signal of the fractional-N PLL and a reference signal. A nonlinear quantization noise cancellation circuit supplies a correction signal to ensure that the generated digital representation has reduced quantization noise. The correctional signal may be applied in the analog or digital domain.

Claims

1. A method comprising:

performing nonlinear quantization noise cancellation to generate a digital representation of a phase error with reduced quantization noise, the phase error corresponding to a time difference between a feedback signal of a fractional-N phase-locked loop (PLL) and a reference signal.

2. The method as recited in claim 1 further comprising:

introducing a non-linear component into an analog phase error representation in a time-to-voltage converter in the PLL.

3. The method as recited in claim 1 further comprising:

performing the nonlinear quantization noise cancellation in an analog domain to generate an analog representation of the phase error with reduced quantization noise; and

converting the analog representation to the digital representation of the phase error with reduced quantization noise.

4. The method as recited in claim 1 wherein performing the nonlinear quantization noise cancellation further comprises multiplying a quantization error based signal by a polynomial and supplying a multiplied signal, the quantization error based signal based on a residue signal from a first delta sigma modulator controlling a divider value for a feedback divider in the fractional-N PLL.

5. The method as recited in claim 4 further comprising:

updating coefficient values of the polynomial with a first update time period during initial operation of the quantization noise cancellation; and

updating the coefficient values of the polynomial with a second update time period greater than the first update time period during steady state operation of the quantization noise cancellation.

6. The method as recited in claim 4 further comprising forming the quantization error based signal by summing a dither signal with the residue signal.

7. The method as recited in claim 4 wherein the polynomial is a third order polynomial.

8. The method as recited in claim 4 further comprising:

supplying the multiplied signal to a second delta sigma modulator and generating a quantized version of the multiplied signal and a second residue signal corresponding to a residual error of a digital to analog converter;

supplying the quantized version of the multiplied signal to the digital to analog converter and generating an analog representation of the quantized version of the multiplied signal;

combining the analog representation of the quantized version of the multiplied signal with an analog representation of the phase error to reduce quantization noise in the analog representation; and

supplying the analog representation with reduced quantization noise to an analog to digital converter and generating the digital representation of the phase error.

9. The method as recited in claim 8 further comprising:

combining a first signal based on the second residue signal with a second signal corresponding to the digital representation of the phase error to generate a second digital representation of the phase error with further reduced quantization noise; and

controlling a frequency of an oscillator of the fractional-N PLL based on the second digital representation of the phase error.

10. The method as recited in claim 9 further comprising:

generating the second signal using a compensation filter to compensate for memory effect of a capacitor filter formed by capacitors used in sampling the analog representation of the phase error with reduced quantization noise.

11. The method as recited in claim 10 further comprising:

setting the quantized version of the multiplied signal to a constant value so as to have no dynamic effect on the phase error signal; and

determining coefficient values of the compensation filter with the quantized version of the multiplied signal set to the constant value.

12. The method as recited in claim 1 further comprising:

generating an analog representation of the phase error;

converting the analog representation to a digital representation; and

performing the nonlinear quantization noise cancellation in a digital domain after converting to the digital representation.

13. A fractional-N phase-locked loop (PLL) comprising:

a nonlinear time to digital converter to generate a digital representation of a phase error corresponding to a time difference between a feedback signal of the fractional-N PLL and a reference signal; and

a nonlinear quantization noise cancellation circuit coupled to supply a correction signal to the time to digital converter to cause the time to digital converter to generate the digital representation of the phase error with reduced quantization noise.

14. The fractional-N PLL as recited in claim 13 wherein the nonlinear time to digital converter further comprises:

a resistor-based or current-based charge pump controlled by a phase detector to create a voltage corresponding to the phase error that is combined with the correction signal; and

an analog to digital converter to generate the digital representation of the phase error with reduced quantization noise.

15. The fractional-N PLL as recited in claim 14 further comprising:

a delta sigma modulator supplying a divider control signal for the fractional-N PLL and a first residue signal corresponding to a quantization error associated with the delta sigma modulator;

a feedback divider coupled to receive the divider control signal and an output of a controlled oscillator of the PLL and supply the feedback signal; and

wherein the nonlinear quantization noise cancellation circuit includes a multiplier circuit to multiply a quantization error signal by a polynomial and supply a multiplied signal, the quantization error signal based on the first residue signal.

16. The fractional-N PLL as recited in claim 15 wherein the nonlinear quantization noise cancellation circuit is configured to update coefficient values of the polynomial with a first update time period during a period of operation of the quantization noise cancellation and is configured to update the coefficient values of the polynomial with a second update time period during another period of operation, the second update time period being greater than the first update time period.

17. The fractional-N PLL as recited in claim 15 further comprising a summing circuit coupled to sum a dither signal with the residue signal to generate the quantization error signal.

18. The fractional-N PLL as recited in claim 15 wherein the polynomial is a third order polynomial.

19. The fractional-N PLL as recited in claim 15 further comprising:

a second delta sigma modulator coupled to receive the multiplied signal and to generate a quantized version of the multiplied signal and a second residue signal;

a digital to analog converter coupled to receive the quantized version of the multiplied signal and generate an analog representation of the quantized version of the multiplied signal as the correction signal; and

wherein the analog representation of the quantized version of the multiplied signal and the voltage corresponding to the phase error are combined in the time to digital converter to generate an analog representation of the phase error with reduced quantization noise.

20. The fractional-N PLL as recited in claim 19 further comprising a summing circuit coupled to combine a first signal based on the second residue signal and a second signal based on the digital representation of the phase error, to generate a residual phase error signal having further reduced quantization error.

21. The fractional-N PLL as recited in claim 20 further comprising a compensation filter coupled to the digital representation of the phase error and configured to compensate for memory effect of a capacitor filter formed by capacitors used in sampling the analog representation of the phase error and the compensation filter being further coupled to supply the second signal to the summing circuit.

22. A fractional-N phase-locked loop (PLL) comprising:

a nonlinear time to digital converter to generate a digital representation of a phase error corresponding to a time difference between a feedback signal of the fractional-N PLL and a reference signal, the digital representation including nonlinearity and quantization noise;

a nonlinear quantization noise cancellation circuit coupled to supply a correction signal to reduce the quantization noise; and

a summing circuit to combine the correction signal and a second signal based on the digital representation of the phase error, to generate a second digital representation of the phase error with reduced quantization noise.

23. The fractional-N PLL as recited in claim 22 further comprising:

a delta sigma modulator supplying a divider control signal for the fractional-N PLL and a first residue signal corresponding to the quantization error associated with the delta sigma modulator;

a feedback divider coupled to receive the divider control signal and an output of a controlled oscillator of the PLL and supply the feedback signal; and

wherein the nonlinear quantization noise cancellation circuit includes a multiplier circuit to multiply a quantization error signal by a polynomial and supply a multiplied signal as the correction signal, the quantization error signal based on the first residue signal.