HIGH FREQUENCY SEMICONDUCTOR SWITCH CIRCUIT AND HIGH FREQUENCY RADIO SYSTEM INCLUDING SAME

• US 20150145587A1
• Filed: 02/02/2015
• Published: 05/28/2015
• Est. Priority Date: 08/09/2012
• Status: Active Grant

• Current Assignee: Panasonic Semiconductor Solutions Co., Ltd. (Winbond Electronics Corporation)
• Original Assignee: Panasonic Intellectual Property Management Co., Ltd. (Panasonic Holdings Corporation)
• Inventors: MIYAZAKI, Takahito, NOZAKI, Yusuke, FUKUSEN, Masaru, SIGETANI, Atusi
• Granted Patent: US 9,312,853 B2
• Time in Patent Office: Days
• US Class Current: 327/382
• CPC Class Codes: H03K 17/162 without feedback from the output circuit to the control circuit
• CPC Class Codes: H03K 17/6877 the control circuit comprising active elements different from those used in the output circuit
• CPC Class Codes: H03K 17/689 with galvanic isolation between the control circuit and the output circuit H03K17/78 takes precedence
• CPC Class Codes: H03K 17/693 Switching arrangements with several input- or output-terminals, e.g. multiplexers, distributors logic circuits H03K19/00; code converters H03M5/00, H03M7/00
• CPC Class Codes: H03K 2017/066 Maximizing the OFF-resistance instead of minimizing the ON-resistance
• CPC Class Codes: H03K 2217/0054 Gating switches, e.g. pass gates
• CPC Class Codes: H04B 1/48 in circuits for connecting transmitter and receiver to a common transmission path, e.g. by energy of transmitter H04B1/46 takes precedence

Abstract

A path switching FET and a shunt FET are separated from each other by a capacitor. The gates of the path switching FET and the shunt FET are controlled using an inverter circuit having a first internal power supply voltage (e.g., 2.5 V) as a power supply. The sources and drains of the path switching FET and the shunt FET are controlled using an inverter circuit having a second internal power supply voltage (e.g., 1.25 V) which is smaller than the first internal power supply voltage, as a power supply.

Claims

1. A high-frequency semiconductor switch circuit comprising:

one common input/output terminal, two or more separate input/output terminals, and two or more control terminals corresponding to the separate input/output terminals;

two or more path switching FET blocks, one block being provided between the common input/output terminal and each of the two or more separate input/output terminals;

one or more shunt FET blocks, one block being provided between the ground and each of at least one of the two or more separate input/output terminals;

a direct-current blocking capacitor provided at both ends of each of the two or more path switching FET blocks;

a direct-current blocking capacitor provided at both ends of each of the one or more shunt FET blocks; and

a source bias resistor provided for each of the two or more path switching FET blocks and for each of the one or more shunt FET blocks, wherein

a control voltage input to each of the two or more control terminals is applied to the gate of a corresponding one of the two or more path switching FET blocks so that at least one of high-frequency signal paths between the common input/output terminal and the respective separate input/output terminals is caused to be in the conducting state while the other high-frequency signal paths are caused to be in the non-conducting state,

a control voltage which is an inverted version of a voltage input to each of the two or more control terminals is applied to the gate of a corresponding one of the one or more shunt FET blocks,

a control voltage which has an inverted polarity and a smaller absolute value compared to a voltage input to each of the two or more control terminals, is applied to the source or drain of a corresponding one of the two or more path switching FET blocks, and

a control voltage which has a non-inverted polarity and a smaller absolute value compared to a voltage input to each of the two or more control terminals, is applied to the source or drain of a corresponding one of the one or more shunt FET blocks.

2. The high-frequency semiconductor switch circuit of claim 1, further comprising:

an inverter circuit configured to have a first internal power supply voltage as a power supply voltage; and

an inverter circuit configured to have a second internal power supply voltage having a value smaller than that of the first internal power supply voltage as a power supply voltage, wherein

a control voltage input to each of the two or more control terminals is applied to the gate of a corresponding one of the two or more path switching FET blocks, through a cascade of two inverter circuits having the first internal power supply voltage as a power supply voltage or a circuit having the same logic as that of the cascade of two inverter circuits, so that at least one of high-frequency signal paths between the common input/output terminal and the respective separate input/output terminals is caused to be in the conducting state while the other high-frequency signal paths are caused to be in the non-conducting state,

a control voltage input to each of the two or more control terminals is applied to the gate of a corresponding one of the one or more shunt FET blocks through a single inverter circuit having the first internal power supply voltage as a power supply voltage or a circuit having the same logic as that of the single inverter circuit,

a control voltage input to each of the two or more control terminals is applied to the source of a corresponding one of the two or more path switching FET blocks through a single inverter circuit having the second internal power supply voltage as a power supply voltage or a circuit having the same logic as that of the single inverter circuit, and

a control voltage input to each of the two or more control terminals is applied to the source of a corresponding one of the one or more shunt FET blocks through a cascade of two inverter circuits having the second internal power supply voltage as a power supply voltage or a circuit having the same logic as that of the cascade of two inverter circuits.

3. The high-frequency semiconductor switch circuit of claim 1, further comprising:

an inverter circuit; and

a voltage division resistor,

wherein

a control voltage input to each of the two or more control terminals is applied to the gate of a corresponding one of the two or more path switching FET blocks, through a cascade of two inverter circuits or a circuit having the same logic as that of the cascade of two inverter circuits, so that at least one of high-frequency signal paths between the common input/output terminal and the respective separate input/output terminals is caused to be in the conducting state while the other high-frequency signal paths are caused to be in the non-conducting state,

a control voltage input to each of the two or more control terminals is applied to the gate of a corresponding one of the one or more shunt FET blocks through a single inverter circuit or a circuit having the same logic as that of the single inverter circuit,

a control voltage input to each of the two or more control terminals is passed through a single inverter circuit or a circuit having the same logic as that of the single inverter circuit, and divided using the voltage division resistor, to obtain a division control voltage, and the division control voltage is applied to the source of a corresponding one of the two or more path switching FET blocks, and

a control voltage input to each of the two or more control terminals is passed through a cascade of two inverter circuits or a circuit having the same logic as that of the cascade of two inverter circuits, and divided using the voltage division resistor, to obtain a division control voltage, and the division control voltage is applied to the source of a corresponding one of the one or more shunt FET blocks.

4. The high-frequency semiconductor switch circuit of claim 1, wherein

the semiconductor substrate is an SOI substrate or an SOS substrate.

5. The high-frequency semiconductor switch circuit of claim 1, wherein

the two or more path switching FET blocks each include a plurality of MOSFET connected together in series.

6. The high-frequency semiconductor switch circuit of claim 1, wherein

the one or more shunt FET blocks each include a plurality of MOSFET connected together in series.

7. A high-frequency radio system comprising:

the high-frequency semiconductor switch circuit of claim 1.