PARTIAL ACCESS MODE FOR DYNAMIC RANDOM ACCESS MEMORY
First Claim
1. A device comprising:
- a plurality of memory cells; and
a controller controlling storage of data in the plurality of memory cells, the controller configured to operate a first access mode which stores one bit data into 1 cell of the memory cells, and a second access mode which stores one bit data into 2N cells of the memory cells, wherein N is a natural number.
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Abstract
Some embodiments provide a method to reduce the refresh power consumption by effectively extending the memory cell retention time. Conversion from 1 cell/bit to 2N cells/bit reduces the variation in the retention time among memory cells. The conversion can be realized very simply from the structure of the DRAM array circuit, and it reduces the frequency of disturbance and power consumption by two orders of magnitude. On the basis of this conversion method, some embodiments provide a partial access mode to reduce power consumption dynamically when the full memory capacity is not required. One bit data may be stored into 1 cell for a normal operation mode and stored into 2N cells for a self refresh operation mode for a first partial access mode, while one bit data may be stored into 2N cells for both normal and self refresh operation modes.
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Citations
19 Claims
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1. A device comprising:
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a plurality of memory cells; and a controller controlling storage of data in the plurality of memory cells, the controller configured to operate a first access mode which stores one bit data into 1 cell of the memory cells, and a second access mode which stores one bit data into 2N cells of the memory cells, wherein N is a natural number. - View Dependent Claims (2, 3, 4, 5, 6, 7)
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8. A device comprising:
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a plurality of memory cells; and a controller controlling storage of data in the plurality of memory cells, the controller configured to store data in the plurality of memory cells as 1 data bit/cell for a normal operation mode and store data in the plurality of memory cells as 1 data bit/2N cells for a self refresh operation mode in a first partial access mode, and further configured to store data in the plurality of memory cells as 1 data bit/2N cells for both a normal operation mode and a self refresh operation mode in a second partial access mode. - View Dependent Claims (9, 10, 11)
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12. A method for managing storage of data in a device, the method comprising:
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storing one bit data into 1 cell of the memory cells when operating in a first access mode; and storing one bit data into 2N cells of the memory cells when operating in a second access mode, wherein N is a natural number. - View Dependent Claims (13, 14, 15, 16, 17, 18, 19)
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Specification