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TRANSLATION LAYER IN A SOLID STATE STORAGE DEVICE

  • US 20150149712A1
  • Filed: 02/05/2015
  • Published: 05/28/2015
  • Est. Priority Date: 10/13/2008
  • Status: Active Grant
First Claim
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1. A solid state device comprising:

  • a controller;

    wherein the controller is configured to generate a data block look-up table comprising a logical block address in a memory array, wherein the logical block address in the memory array is associated with a data block look-up table entry that comprises a first portion configured to indicate a highest programmed page of a physical memory block indicated by the logical block address and a second portion that is different from the first portion and that is configured to indicate that the physical memory block is ordered when the physical memory block is ordered and to indicate that the physical memory block is not ordered when the physical memory block is not ordered.

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