TRANSLATION LAYER IN A SOLID STATE STORAGE DEVICE

• US 20150149712A1
• Filed: 02/05/2015
• Published: 05/28/2015
• Est. Priority Date: 10/13/2008
• Status: Active Grant

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: Manning, Troy
• Granted Patent: US 9,176,868 B2
• Time in Patent Office: Days
• US Class Current: 711/103
• CPC Class Codes: G06F 12/0246 in block erasable memory, e.g. flash memory
• CPC Class Codes: G06F 12/0292 using tables or multilevel address translation means G06F12/023 takes precedence; address translation in virtual memory systems G06F12/10
• CPC Class Codes: G06F 2212/1044 Space efficiency improvement
• CPC Class Codes: G06F 2212/1048 Scalability
• CPC Class Codes: G06F 2212/2022 Flash memory
• CPC Class Codes: G06F 2212/7201 Logical to physical mapping or translation of blocks or pages
• CPC Class Codes: G06F 2212/7208 Multiple device management, e.g. distributing data over multiple flash devices
• CPC Class Codes: G11C 16/102 External programming circuits, e.g. EPROM programmers; In-circuit programming or reprogramming; EPROM emulators
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

Solid state storage devices and methods for flash translation layers are disclosed. In one such translation layer, a sector indication is translated to a memory location by a parallel unit look-up table is populated by memory device enumeration at initialization. Each table entry is comprised of communication channel, chip enable, logical unit, and plane for each operating memory device found. When the sector indication is received, a modulo function operates on entries of the look-up table in order to determine the memory location associated with the sector indication.

Claims

1. A solid state device comprising:

a controller;

wherein the controller is configured to generate a data block look-up table comprising a logical block address in a memory array, wherein the logical block address in the memory array is associated with a data block look-up table entry that comprises a first portion configured to indicate a highest programmed page of a physical memory block indicated by the logical block address and a second portion that is different from the first portion and that is configured to indicate that the physical memory block is ordered when the physical memory block is ordered and to indicate that the physical memory block is not ordered when the physical memory block is not ordered.

2. The solid state device of claim 1, wherein when the physical memory block is ordered, the logical block address comprises a number of a page within the physical memory block and a position in that page.

3. The solid state device of claim 1, wherein data block look-up table entry comprises a third portion that points to the physical block.

4. The solid state device of claim 1, wherein the controller is configured to determine a location of the memory array in response to a sector request that comprises a sector number that is the logical block address.

5. The solid state device of claim 4, wherein sector request comprises a read command or a write command.

6. The solid state device of claim 1, wherein the logical address corresponds to a portion of a page of the physical memory block.

7. The solid state device of claim 1, wherein the controller is configured to generate a location of the memory device by shifting the logical block address a plurality of times in response to a quantity of logical block addresses per page of the physical memory block.

8. The solid state device of claim 1, wherein the controller is configured to determine a location of the memory device from a memory array table in response to receiving the logical block address.

9. The solid state device of claim 1, wherein the controller comprises a Flash Translation Layer.

10. The solid state device of claim 1, wherein the controller is configured to locate the physical block in the data block look-up table in response to the logical block address.

11. A solid state device, comprising:

a controller;

wherein the controller is configured to determine the existence of parallel units within the solid state device;

wherein the controller is configured to determine a location of a target parallel unit that is determined to exist within the solid state device; and

wherein the controller is configured to generate a data block look-up table comprising a group of logical block addresses in the target parallel unit, each logical block address associated with a different data block look-up table entry, each entry comprising a first portion configured to indicate a highest programmed page of a memory block indicated by the associated logical block address and a second portion that is different from the first portion and that is configured to indicate that the memory block is ordered when the memory block is ordered and to indicate that the memory block is not ordered when the memory block is not ordered.

12. The solid state device of claim 11, wherein the controller being configured to determine the location of the target parallel unit within the solid state device comprises the controller being configured to determine the location of the target parallel unit within the solid state device from a parallel unit look-up table.

13. The solid state device of claim 12, wherein the controller being configured to determine the location of the target parallel unit within the solid state device from the parallel unit look-up table comprises the controller being configured to determine an index for the target parallel unit and finding location characteristics for the target parallel unit from a location in the table identified by the index for the target parallel unit.

14. The solid state device of claim 13, wherein the controller being configured to determine the index for the target parallel unit comprises the controller being configured to determine the index for the target parallel unit based on a number of parallel units determined to exist within the solid state device and a number of logical addresses per page of the memory block indicated by the associated logical block address.

15. The solid state device of claim 11, wherein the controller is configured to generate a parallel unit look-up table that comprises location information for each of the parallel units determined to exist within the solid state device.

16. The solid state device of claim 15, wherein the controller is configured to store the parallel unit look-up table in RAM of the solid state device.

17. The solid state device of claim 15, wherein the controller is configured to store the parallel unit look-up table in a memory block of a parallel unit determined to exist within the solid state device.

18. The solid state device of claim 17, wherein the controller being configured to store the parallel unit look-up table in the memory block of the parallel unit determined to exist within the solid state device comprises the controller being configured to store the parallel unit look-up table in a memory block that is determined to be free of errors.

19. A method of operating solid state device, the method comprising:

determining a location of a memory device within the solid state device from location characteristics for the memory device that are at a location in a memory device table, wherein the location in the memory device table is identified by an index for the memory device; and

generating a data block look-up table comprising a logical block address in the memory device, wherein the logical block address in the memory device is associated with a data block look-up table entry that comprises a first portion configured to indicate a highest programmed page of a physical memory block indicated by the logical block address and a second portion that is different from the first portion and that is configured to indicate that the physical memory block is ordered when the physical memory block is ordered and to indicate that the physical memory block is not ordered when the physical memory block is not ordered.

20. The method of claim 19, further comprising generating the memory device table.

21. The method of claim 19, further comprising receiving the logical block address from a host.

22. The method of claim 21, further comprising determining the index for the memory device from the logical block address based on a number of memory devices in the memory device table and a number of logical block addresses per page of the physical memory block.

23. The method of claim 22, further comprising shifting the logical block address to account for the number of logical block addresses per page of the physical memory block.