PARTIAL ACCESS MODE FOR DYNAMIC RANDOM ACCESS MEMORY

• US 20150149717A1
• Filed: 01/30/2014
• Published: 05/28/2015
• Est. Priority Date: 11/26/2013
• Status: Active Grant

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Elpida Memory Incorporated (Micron Technology, Inc.)
• Inventors: RIHO, Yoshiro
• Granted Patent: US 9,640,240 B2
• Time in Patent Office: Days
• US Class Current: 711/106
• CPC Class Codes: G11C 11/40615 Internal triggering or timing of refresh, e.g. hidden refresh, self refresh, pseudo-SRAMs
• CPC Class Codes: G11C 11/40622 Partial refresh of memory arrays

Abstract

Some embodiments provide a method to reduce the refresh power consumption by effectively extending the memory cell retention time. Conversion from 1 cell/bit to 2^N cells/bit reduces the variation in the retention time among memory cells. Although active power increases by a factor of 2^N, the refresh time increases by more than 2^N as a consequence of the fact that the majority decision does better than averaging for the tail distribution of retention time. The conversion can be realized very simply from the structure of the DRAM array circuit, and it reduces the frequency of disturbance and power consumption by two orders of magnitude. On the basis of this conversion method, some embodiments provide a partial access mode to reduce power consumption dynamically when the full memory capacity is not required.

Claims

1. A device comprising:

a plurality of memory banks; and

a controller controlling storage of data in cells of the plurality of memory banks,

wherein the controller copies each bit of data stored in the plurality of memory banks that is to be preserved from 1 cell per bit to 2^N cells per bit, where N is a natural number.

2. The device of claim 1, wherein the controller copying causes the effective retention time of each bit of data copied to be extended.

3. The device of claim 2, wherein the effective retention time of each bit of data copied is extended by a factor of 2^N.

4. The device of claim 1, wherein the controller copying causes the power consumption of the memory module to be reduced.

6. The device of claim 1, wherein N=4.

7. The device of claim 1, wherein a portion of each memory bank of the plurality of memory banks is active when the memory module is in a self refresh mode of operation.

5. The device of claim 5, wherein the controller can reduce the power consumption of the device by copying each bit of data stored in the plurality of memory banks that is to be preserved from 1 cell per bit to 2^N cells per bit in both a normal operation mode and a self refresh operation mode.

8. A method for managing storage of data in a device, the method comprising:

storing at least one bit of data in at least one cell of the device, wherein each bit of data is stored in a single cell of the device; and

copying a portion of the at least one bit of data into 2^N cells of the device.

9. The method of claim 8, wherein the step of copying causes the effective retention time of each bit of data copied to be extended.

10. The method of claim 9, wherein the effective retention time of each bit of data copied is extended by a factor of 2^N.

11. The method of claim 8, wherein the step of copying allows the power consumption of the device to be reduced.

12. The method of claim 11, wherein the power consumption of the device can be reduced by the step of copying in both a normal operation mode and a self refresh operation mode.

13. The method of claim 8, wherein N=4.

14. The method of claim 8, wherein the at least one cell of the device is spread across a plurality of memory banks of the memory module, and a portion of each memory bank of the plurality of memory banks is active when the device is in a self refresh mode of operation.