VOLTAGE REGULATOR TRAINING
First Claim
Patent Images
1. An apparatus comprising:
- an analog front end (AFE); and
a voltage regulator coupled with the AFE, the voltage regulator configured to supply a voltage to the AFE;
wherein the voltage regulator is configured to dynamically alter the voltage to reduce power consumption of the AFE based at least in part on a result of a training loop performed on system power up or system reset.
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Abstract
Embodiments including systems, methods, and apparatuses associated with increasing the power efficiency of one or more components of a computing system. Specifically, the system may include a processor chip which may include an on-die voltage regulator (VR) configured to supply a voltage to a component of the processor chip. The processor chip may be coupled with a dynamic random access memory (DRAM). The system may further include an external VR coupled with the DRAM. A BIOS may be configured to regulate the voltage output of one or both of the on-die VR and/or the external VR. Other embodiments may be described or claimed.
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Citations
20 Claims
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1. An apparatus comprising:
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an analog front end (AFE); and a voltage regulator coupled with the AFE, the voltage regulator configured to supply a voltage to the AFE; wherein the voltage regulator is configured to dynamically alter the voltage to reduce power consumption of the AFE based at least in part on a result of a training loop performed on system power up or system reset. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8)
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9. A method comprising:
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setting, by a basic input/output system (BIOS), a voltage output of an on-die voltage regulator to a first voltage; identifying, by the BIOS, an occurrence of a margin failure at an analog front end (AFE) configured to receive the first voltage; and adjusting, by the BIOS in response to the occurrence of the margin failure, the voltage output of the on-die voltage regulator by an increment. - View Dependent Claims (10, 11, 12, 13, 14, 15)
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16. A system comprising:
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a memory controller coupled with a dynamic random access memory (DRAM); an on-die voltage regulator to supply a first voltage to an analog front end (AFE) coupled with the DRAM; an external voltage regulator configured to supply a second voltage to the DRAM; wherein the on-die voltage regulator and the external voltage regulator are configured to alter the first voltage or the second voltage based at least in part on a signal from a basic input/output system (BIOS). - View Dependent Claims (17, 18, 19, 20)
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Specification