DEFECT MANAGEMENT POLICIES FOR NAND FLASH MEMORY

• US 20150149818A1
• Filed: 11/22/2013
• Published: 05/28/2015
• Est. Priority Date: 11/22/2013
• Status: Active Grant

• Current Assignee: SK Hynix NAND Product Solutions Corporation (SK Hynix Inc.)
• Original Assignee: Intel Corporation
• Inventors: Kalavade, Pranav, Zhu, Feng, Raghunathan, Shyam Sunder, Motwani, Ravi H.
• Granted Patent: US 9,535,777 B2
• Time in Patent Office: Days
• US Class Current: 714/6.13
• CPC Class Codes: G06F 11/073 in a memory management context, e.g. virtual memory or cache management memory management G06F12/00; testing of static memory units G11C29/00
• CPC Class Codes: G06F 11/0751 Error or fault detection not based on redundancy power supply failures G06F1/30; network fault management H04L41/06
• CPC Class Codes: G06F 11/1012 using codes or arrangements adapted for a specific type of error G06F11/1048 takes precedence
• CPC Class Codes: G11B 20/1816 Testing

Abstract

Systems and methods of managing defects in nonvolatile storage systems that can be used to avoid an inadvertent loss of data, while maintaining as much useful memory in the nonvolatile storage systems as possible. The disclosed systems and methods can monitor a plurality of trigger events for detecting possible defects in one or more nonvolatile memory (NVM) devices included in the nonvolatile storage systems, and apply one or more defect management policies to the respective NVM devices based on the types of trigger events that resulted in detection of the possible defects. Such defect management policies can be used proactively to retire memory in the nonvolatile storage systems with increased granularity, focusing the retirement of memory on regions of nonvolatile memory that are likely to contain a defect.

Claims

1. A method of managing defects in a nonvolatile storage system, the nonvolatile storage system including one or more nonvolatile memory (NVM) devices, the method comprising:

monitoring, by an NVM defect management policy engine, a plurality of trigger events for detecting possible defects in at least one NVM device, each of the plurality of trigger events having an associated type;

having monitored at least one trigger event, determining the type of the trigger event by the NVM defect management policy engine; and

applying, by the NVM defect management policy engine, at least one defect management policy to the NVM device based on the type of the trigger event.

2. The method of claim 1 wherein the type of the trigger event includes one or more of a soft bit read trigger event and an exclusive- or (XOR) data recovery trigger event, and wherein the applying of the at least one defect management policy to the NVM device includes retiring an NVM storage location of a codeword for which a host processor issued a data read request.

3. The method of claim 2 wherein the type of the trigger event includes one or more of the soft bit read trigger event and the XOR data recovery trigger event, and wherein the applying of the at least one defect management policy to the NVM device includes retiring a physical memory page that includes the NVM storage location of the codeword for which the host processor issued the data read request.

4. The method of claim 1 wherein the type of the trigger event includes a predetermined number of hard bit read trigger events, and wherein the applying of the at least one defect management policy to the NVM device includes retiring an NVM storage location of a codeword for which a host processor issued one or more data read requests.

5. The method of claim 4 wherein the type of the trigger event includes the predetermined number of hard bit read trigger events, and wherein the applying of the at least one defect management policy to the NVM device includes retiring a physical memory page that includes the NVM storage location of the codeword for which the host processor issued the data read requests.

6. The method of claim 5 further comprising:

in the event a region of nonvolatile memory containing the physical memory page is to be programmed, programming a predetermined random pattern of data onto the physical memory page.

7. The method of claim 5 wherein the retiring of the physical memory page includes retiring a group of pages.

8. The method of claim 5 wherein the retiring of the physical memory page includes retiring a same page in a plurality of blocks in one or more of the NVM devices.

9. A nonvolatile storage system, comprising:

a nonvolatile memory (NVM) controller;

one or more NVM devices communicably coupled to the NVM controller; and

an NVM defect management policy engine communicably coupled to the NVM controller, wherein the NVM defect management policy engine is operative;

to monitor a plurality of trigger events for detecting possible defects in at least one NVM device, each of the plurality of trigger events having an associated type;

having monitored at least one trigger event, to determine the type of the trigger event; and

to apply at least one defect management policy to the NVM device based on the type of the trigger event.

10. The system of claim 9 wherein the type of the trigger event includes one or more of a soft bit read trigger event and an exclusive- or (XOR) data recovery trigger event, and wherein the NVM defect management policy engine is further operative, having monitored the soft bit read trigger event or the XOR data recovery trigger event, to retire an NVM storage location of a codeword for which a host processor issued a data read request.

11. The system of claim 10 wherein the type of the trigger event includes one or more of the soft bit read trigger event and the XOR data recovery trigger event, and wherein the NVM defect management policy engine is further operative, having monitored the soft bit read trigger event or the XOR data recovery trigger event, to retire a physical memory page that includes the NVM storage location of the codeword for which the host processor issued the data read request.

12. The system of claim 9 wherein the type of the trigger event includes a predetermined number of hard bit read trigger events, and wherein the NVM defect management policy engine is further operative, having monitored the predetermined number of hard bit read trigger events, to retire an NVM storage location of a codeword for which a host processor issued one or more data read requests.

13. The system of claim 12 wherein the type of the trigger event includes the predetermined number of hard bit read trigger events, and wherein the NVM defect management policy engine is further operative, having monitored the predetermined number of hard bit read trigger events, to retire a physical memory page that includes the NVM storage location of the codeword for which the host processor issued the data read requests.

14. The system of claim 13 wherein the NVM controller is operative, in the event a region of nonvolatile memory containing the physical memory page is to be programmed, to control programming of a predetermined random pattern of data onto the physical memory page.

15. A computer system, comprising:

a system bus;

a memory bus;

a display communicably coupled to the system bus;

at least one volatile memory coupled to the system bus; and

the nonvolatile storage system of claim 9 communicably coupled to the memory bus.

16. A nonvolatile storage system including one or more nonvolatile memory (NVM) devices, the system comprising:

means for monitoring a plurality of trigger events for detecting possible defects in at least one NVM device, each of the plurality of trigger events having an associated type;

having monitored at least one trigger event, means for determining the type of the trigger event; and

means for applying at least one defect management policy to the NVM device based on the type of the trigger event.

17. The system of claim 16 wherein the type of the trigger event includes one or more of a soft bit read trigger event and an exclusive- or (XOR) data recovery trigger event, and wherein the system further comprises:

having monitored the soft bit read trigger event or the XOR data recovery trigger event, means for retiring an NVM storage location of a codeword for which a host processor issued a data read request.

18. The system of claim 17 wherein the type of the trigger event includes one or more of the soft bit read trigger event and the XOR data recovery trigger event, and wherein the system further comprises:

having monitored the soft bit read trigger event or the XOR data recovery trigger event, means for retiring a physical memory page that includes the NVM storage location of the codeword for which the host processor issued the data read request.

19. The system of claim 16 wherein the type of the trigger event includes a predetermined number of hard bit read trigger events, and wherein the system further comprises:

having monitored the predetermined number of hard bit read trigger events, means for retiring an NVM storage location of a codeword for which a host processor issued one or more data read requests.

20. The system of claim 19 wherein the type of the trigger event includes the predetermined number of hard bit read trigger events, and wherein the system further comprises:

having monitored the predetermined number of hard bit read trigger events, means for retiring a physical memory page that includes the NVM storage location of the codeword for which the host processor issued the data read requests.

21. A computer-readable storage medium including executable instructions for accessing data storable within a non-volatile memory (NVM) device in a computer system, the computer system including at least one processor, the computer-readable storage medium comprising executable instructions:

to monitor a plurality of trigger events for detecting possible defects in at least one NVM device, each of the plurality of trigger events having an associated type;

having monitored at least one trigger event, to determine the type of the trigger event; and

to apply at least one defect management policy to the NVM device based on the type of the trigger event.