MEMORY AND MEMORY MODULE INCLUDING THE SAME

• US 20150149820A1
• Filed: 02/27/2014
• Published: 05/28/2015
• Est. Priority Date: 11/27/2013
• Status: Active Grant

• Current Assignee: MIMIRIP LLC (Ideahub, Inc.)
• Original Assignee: SK Hynix Inc.
• Inventors: SONG, Choung-Ki
• Granted Patent: US 9,298,558 B2
• Time in Patent Office: Days
• US Class Current: 714/14
• CPC Class Codes: G06F 11/1441 Resetting or repowering
• CPC Class Codes: G06F 11/1456 Hardware arrangements for backup
• CPC Class Codes: G06F 11/2002 where interconnections or communication control functionality are redundant flexible arrangements for bus networks involving redundancy H04L12/40176
• CPC Class Codes: G06F 11/2005 using redundant communication controllers
• CPC Class Codes: G06F 11/2007 using redundant communication media
• CPC Class Codes: G06F 11/201 between storage system components
• CPC Class Codes: G06F 11/2017 where memory access, memory control or I/O control functionality is redundant redundant communication control functionality G06F11/2005; redundant storage control functionality G06F11/2089

Abstract

A memory unit including a first data transferring/receiving unit suitable for transferring/receiving data through a first data bus for communication with a host, a second data transferring/receiving unit suitable for transferring/receiving data through a second data bus for a data backup, and a control unit suitable for controlling the first data transferring/receiving unit and the second data transferring/receiving unit to be activated or inactivated according to whether a power failure occurs in the host.

Claims

1. A memory unit, comprising:

a first data transferring/receiving unit suitable for transferring/receiving data through a first data bus for communication with a host;

a second data transferring/receiving unit suitable for transferring/receiving data through a second data bus for a data backup; and

a control unit suitable for controlling the first data transferring/receiving unit and the second data transferring/receiving unit to be activated or inactivated according to whether a power failure occurs.

2. The memory unit of claim 1, wherein the control unit activates the first data transferring/receiving unit when a power supply is in a normal state, and activates the second data transferring/receiving unit when the power failure occurs.

3. The memory unit of claim 1, wherein the memory operates using an emergency power when the power failure occurs.

4. The memory unit of claim 1, wherein the first data transferring/receiving unit and the second data transferring/receiving unit transfer and receive a data and a data strobe signal for strobing the data through a corresponding one of the first and second data buses, individually.

5. The memory unit of claim 1, further comprising:

a cell array;

an internal data bus electrically coupled to the cell array; and

a selection unit suitable for allowing the internal data bus to transfer data to and from one of the first and second data transferring/receiving units.

6. The memory unit of claim 1, further comprising:

a command receiving unit suitable for receiving a plurality of command signals;

a command decoding unit suitable for decoding the command signals that are received through the command receiving unit to generate an internal setup command signal, an internal setup reset command signal, and a plurality of internal command signals; and

a setup circuit suitable for performing a setup operation in response to the internal setup command signal and initializing setup values in response to the internal setup reset command signal.

7. A memory module, comprising:

a volatile memory suitable for communicating with a host through a first data bus and transferring and receiving backup data through a second data bus;

a nonvolatile memory suitable for backing up the data of the volatile memory that is transferred through the second data bus when a power failure occurs in the host; and

an emergency power supplier suitable for supplying power for backing up the data of the volatile memory into the nonvolatile memory when the power failure occurs in the host.

8. The memory module of claim 7, further comprising:

a nonvolatile memory controller suitable for controlling the nonvolatile memory; and

a module controller suitable for controlling the volatile memory by using a command, an address, and a clock that are transferred from the host during a normal operation, and controlling the volatile memory and the nonvolatile memory controller to back up the data of the volatile memory into the nonvolatile memory when the power failure occurs in the host.

9. The memory module of claim 8, further comprising:

a power failure detector suitable for detecting the power failure of the host.

10. The memory module of claim 7, wherein the volatile memory includes:

a first data transferring/receiving unit suitable for transferring/receiving a data through the first data bus;

a second data transferring/receiving unit suitable for transferring/receiving a data through a second data bus; and

a control unit suitable for controlling the first data transferring/receiving unit and the second data transferring/receiving unit to be activated or inactivated according to whether a power failure occurs in the host.

11. The memory module of claim 10, wherein the control unit activates the first data transferring/receiving unit when a power supply of the host is in a normal state, and activates the second data transferring/receiving unit when the power failure occurs.

12. The memory module of claim 10, wherein the first data transferring/receiving unit and the second data transferring/receiving unit transfer and receive data and a data strobe signal for strobing the data through a corresponding one of the first and second data buses, individually.

13. The memory module of claim 10, wherein the volatile memory further includes:

a cell array;

an internal data bus electrically coupled to the cell array; and

a selection unit suitable for allowing the internal data bus to transfer data to and from one of the first and second data transferring/receiving units.

14. A memory unit, comprising:

a command receiving unit suitable for receiving a plurality of command signals;

a command decoding unit suitable for decoding the command signals that are received through the command receiving unit to generate an internal setup command signal, an internal setup reset command signal, and a plurality of internal command signals; and

a setup circuit suitable for performing a setup operation in response to the internal setup command signal and initializing setup values in response to the internal setup reset command signal.

15. The memory unit of claim 14, further comprising:

a reset signal receiving unit suitable for receiving a reset signal; and

a plurality of internal circuits that are resettable,

wherein the setup circuit and the internal circuits are initialized when the reset signal is enabled.

16. The memory unit of claim 14, further comprising:

an address receiving unit suitable for receiving a plurality of address signals,

wherein the setup circuit decides a setup value by using all or part of the address signals that are received through the address receiving unit.