AUTOMATIC TESTING SYSTEM AND METHOD

• US 20150153405A1
• Filed: 12/04/2013
• Published: 06/04/2015
• Est. Priority Date: 12/04/2013
• Status: Abandoned Application

• Current Assignee: Princeton Technology Corporation
• Original Assignee: Princeton Technology Corporation
• Inventors: WU, Yung-Yu, CHEN, Huei-Huang
• Application Number:
  US14/096,501
• Publication Number:
  US 20150153405A1
• Time in Patent Office: Days
• US Class Current: 1/1
• CPC Class Codes: G01R 31/2834 Automated test systems [ATE]; using microprocessors or computers G01R31/317 takes precedence; ATE for detection of defective computer hardware G06F11/2736
• CPC Class Codes: G01R 31/3167 Testing of combined analog and digital circuits testing ADC's H03M1/1071
• CPC Class Codes: G01R 31/31919 Storing and outputting test patterns G01R31/31924 takes precedence; arithmetic and random test patterns generator

Abstract

The present invention discloses an automatic testing system. The automatic testing system includes a field programmable gate array (FPGA), a digital-to-analog converter (DAC), an analog-to-digital converter (ADC), and a processor. The FPGA is preprogrammed with a digital signal protocol for testing a DUT. The FPGA generates a digital testing signal in compliance with the digital signal protocol and transmits the digital testing signal to the DUT. The FPGA receives a digital signal output generated by the DUT, analyzes the digital output signal based on the digital signal protocol and obtains a digital test result. The DAC converter generates an analog testing signal to the DUT such that the DUT generates an analog signal output. The ADC measures the analog signal output and gets an analog test result. The processor receives the digital and analog test results and determines whether the functions of the DUT are correct or not.

Claims

1. An automatic testing system, comprising:

a field programmable gate array (FPGA) preprogrammed with a digital signal protocol for testing a device under test (DUT) and configured to generate a digital testing signal in compliance with the digital signal protocol and transmit the digital testing signal to the DUT, receive a digital signal output generated by the DUT in response to the digital testing signal, and analyze the digital signal output based on the digital signal protocol and obtain a digital test result;

a digital-to-analog converter generates an analog testing signal to the DUT such that the DUT generates an analog signal output in response to the analog testing signal;

an analog-to-digital converter measures the analog signal output and obtains an analog test result; and

a processor receives the digital test result and the analog test result and determines whether functions of the DUT are correct or not according to the digital test result and the analog test result.

2. The automatic testing system of claim 1, further comprising a high-speed interface bus, wherein the processor is coupled to the high-speed interface bus and controls the FPGA, the digital-to-analog converter and the analog-to-digital converter via the high-speed interface bus.

3. The automatic testing system of claim 1, further comprising a programmable power supply, which provides the DUT with adjustable power for testing.

4. The automatic testing system of claim 1, wherein ground placements of the processor, the FPGA, the digital-to-analog converter, the analog-to-digital converter and the DUT are configured with a single common ground.

5. The automatic testing system of claim 1, wherein the DUT is an audio integrated circuit.

6. The automatic testing system of claim 1, wherein the FPGA is further preprogrammed with a handshaking protocol and configured to execute a handshaking process with a handler to assign the DUT to perform a specified operation.

7. An automatic testing method, comprising:

providing a field programmable gate array (FPGA), which is preprogrammed with a digital signal protocol for testing a device under test (DUT);

transmitting a digital testing signal generated by the FPGA in compliance with the digital signal protocol to the DUT;

receiving, by the FPGA, a digital signal output which is generated by the DUT in response to the digital testing signal;

analyzing, by the FPGA, the digital signal output based on the digital signal protocol and generating a digital test result;

generating and transmitting, by a digital-to-analog converter, an analog testing signal to the DUT;

generating, by the DUT, an analog signal output according to the analog testing signal;

receiving and measuring, by an analog-to-digital converter, the analog signal output to obtain an analog test result; and

receiving, by a processor, the digital test result and the analog test result and determining whether functions of the DUT are correct or not according to the digital test result and the analog test result.

8. The automatic testing method of claim 7, further comprising providing a high-speed interface bus for the processor to control the FPGA, the digital-to-analog converter, and the analog-to-digital converter.

9. The automatic testing method of claim 7, further comprising configuring ground placements of the processor, the FPGA, the digital-to-analog converter, the analog-to-digital converter, and the DUT with a single common ground.