POWER GATING CIRCUIT AND ELECTRONIC SYSTEM INCLUDING THE SAME

• US 20150153818A1
• Filed: 11/29/2014
• Published: 06/04/2015
• Est. Priority Date: 12/04/2013
• Status: Active Grant

• Current Assignee: Samsung Electronics Co. Ltd. (Samsung Group)
• Original Assignee: Samsung Electronics Co. Ltd. (Samsung Group)
• Inventors: JEON, JAE HAN
• Granted Patent: US 9,329,669 B2
• Time in Patent Office: Days
• US Class Current: 1/1
• CPC Class Codes: G06F 1/189 Power distribution
• CPC Class Codes: G06F 1/26 Power supply means, e.g. regulation thereof for memories G11C
• CPC Class Codes: G06F 1/3203 Power management, i.e. event-based initiation of a power-saving mode
• CPC Class Codes: G06F 1/3243 Power saving in microcontroller unit
• CPC Class Codes: G06F 1/3287 by switching off individual functional units in the computer system
• CPC Class Codes: H03K 19/0016 by using a control or a clock signal, e.g. in order to apply power supply
• CPC Class Codes: H03K 19/017581 programmable
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management
• CPC Class Codes: Y02D 30/50 in wire-line communication networks, e.g. low power modes or reduced link rate

Abstract

A power gating circuit including a first chain buffer that generates a first sleep signal by buffering an input sleep signal, a second chain buffer that generates a second sleep signal by buffering the first sleep signal, and a first switch block including a plurality of first switch cells controlled according to the first sleep signal.

Claims

1. A power gating circuit configured to perform power gating of an element, the power gating circuit comprising:

a first chain buffer that generates a first sleep signal by buffering an input sleep signal received from a power management unit;

a first switch block including a plurality of first switch cells controlled by the first sleep signal;

a second chain buffer that generates a second sleep signal by buffering the first sleep signal; and

a second switch block including a plurality of second switch cells controlled by the second sleep signal, wherein the second sleep signal is returned to the power management unit as an acknowledge signal indicating completion of the power gating of the element.

2. The power gating circuit of claim 1, wherein each of the plurality of first switch cells is a PMOS switch or an NMOS switch.

3. The power gating circuit of claim 1, wherein the power gating circuit has a grid type or ring type switch cell array structure.

4. The power gating circuit of claim 1, wherein a number of the plurality of first switch cells is set according to a maximum transition time violation (MTTV) condition for the second sleep signal.

5. The power gating circuit of claim 1, wherein the power management unit is disposed on a System-on-Chip (SoC) and the element is one of a central processing unit (CPU), a memory controller, and a graphics processing unit (GPU).

6. The power gating circuit of claim 5, wherein a layout implementing the SoC comprises a cell row in a gap between adjacent power rails, and the first chain buffer is disposed adjacent to one of the first switch cells in the cell row.

7. A power gating circuit configured to perform power gating of an element, the power gating circuit comprising:

a first chain buffer that generates a first sleep signal by buffering an input sleep signal received from a power management unit;

a first switch block that receives the first sleep signal;

a second chain buffer that generates a second sleep signal by buffering the first sleep signal; and

a second switch block that receive the second sleep signal,

wherein the first switch block comprises;

a first drive buffer configured to generate a third sleep signal by buffering the first sleep signal and a plurality of first switch cells that receives the third sleep signal,

the second switch block comprises;

a second drive buffer configured to generate a fourth sleep signal by buffering the second sleep signal and a plurality of second switch cells that receives the fourth sleep signal, and

the second sleep signal is returned to the power management unit as an acknowledge signal indicating completion of the power gating of the element.

8. The power gating circuit of claim 7, wherein a size of the first drive buffer is larger than a size of the first chain buffer.

9. The power gating circuit of claim 8, wherein the size of the first drive buffer is larger than a size of the second chain buffer.

10. The power gating circuit of claim 7, wherein a size of the first drive buffer, a size of the first chain buffer, and a number of the plurality of first switch cells are set according to a wire capacity of a wire that connects the first drive buffer with the first chain buffer.

11. The power gating circuit of claim 10, wherein the size of the first drive buffer, the size of the first chain buffer, and the number of the plurality of first switch cells is further set according to drive capacities of the plurality of first switch cells.

12. The power gating circuit of claim 7, wherein a size of the first chain buffer is set according to a number of the plurality of first switch cells.

13. The power gating circuit of claim 7, wherein each of the plurality of first switch cells and each of the plurality of second switch cells is a PMOS switch or an NMOS switch.

14. The power gating circuit of claim 7, wherein the power gating circuit has a grid type or ring type switch cell array structure.

15. The power gating circuit of claim 7, wherein a number of the plurality of first switch cells is set according to a maximum transition time violation (MTTV) condition of the second sleep signal.

16. The power gating circuit of claim 7, wherein the power management unit is disposed on a System-on-Chip (SoC) and the element is one of a central processing unit (CPU), a memory controller, and a graphics processing unit (GPU).

17. The power gating circuit of claim 7, wherein a layout implementing the SoC comprises:

a first cell row in a first gap between first adjacent power rails, the first chain buffer being disposed adjacent to the first drive buffer and the first drive buffer being disposed adjacent one of the first switch cells in the first cell row; and

a second cell row in a second gap between second adjacent power rails, the second chain buffer being disposed adjacent to the second drive buffer and the second drive buffer being disposed adjacent one of the second switch cells in the second cell row.

18. A power gating circuit configured to perform power gating of an element, the power gating circuit comprising:

a first chain buffer that generates a first sleep signal by buffering an input sleep signal received from a power management unit;

a first switch block that receives the first sleep signal;

a second chain buffer that generates a second sleep signal by buffering the first sleep signal; and

a second switch block that receives the second sleep signal,

wherein the first switch block comprises;

a first drive buffer configured to generate a third sleep signal by buffering the first sleep signal and a first plurality of first switch cells that receives the third sleep signal, and

a third drive buffer configured to generate a fifth sleep signal by buffering the first sleep signal and a second plurality of first switch cells that receives the fifth sleep signal, the second switch block comprises;

a second drive buffer configured to generate a second sleep signal by buffering the first sleep signal and a first plurality of second switch cells that receives the second sleep signal, and

a fourth drive buffer configured to generate a sixth sleep signal by buffering the second sleep signal and a second plurality of second switch cells that receives the fifth sleep signal, and

the second sleep signal is returned to the power management unit as an acknowledge signal indicating completion of the power gating of the element.

19. The power gating circuit of claim 18, wherein a size of the first drive buffer is larger than a size of the first chain buffer, and

the size of the first drive buffer is larger than a size of the second chain buffer.

20. The power gating circuit of claim 18, wherein a size of the first drive buffer, a size of the first chain buffer, and a number of the plurality of first switch cells are set according to a wire capacity of a wire that connects the first drive buffer with the first chain buffer, and

the size of the first drive buffer, the size of the first chain buffer, and the number of the plurality of first switch cells is further set according to drive capacities of the plurality of first switch cells.