POWER GATING CIRCUIT AND ELECTRONIC SYSTEM INCLUDING THE SAME
First Claim
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1. A power gating circuit configured to perform power gating of an element, the power gating circuit comprising:
- a first chain buffer that generates a first sleep signal by buffering an input sleep signal received from a power management unit;
a first switch block including a plurality of first switch cells controlled by the first sleep signal;
a second chain buffer that generates a second sleep signal by buffering the first sleep signal; and
a second switch block including a plurality of second switch cells controlled by the second sleep signal, wherein the second sleep signal is returned to the power management unit as an acknowledge signal indicating completion of the power gating of the element.
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Abstract
A power gating circuit including a first chain buffer that generates a first sleep signal by buffering an input sleep signal, a second chain buffer that generates a second sleep signal by buffering the first sleep signal, and a first switch block including a plurality of first switch cells controlled according to the first sleep signal.
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Citations
20 Claims
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1. A power gating circuit configured to perform power gating of an element, the power gating circuit comprising:
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a first chain buffer that generates a first sleep signal by buffering an input sleep signal received from a power management unit; a first switch block including a plurality of first switch cells controlled by the first sleep signal; a second chain buffer that generates a second sleep signal by buffering the first sleep signal; and a second switch block including a plurality of second switch cells controlled by the second sleep signal, wherein the second sleep signal is returned to the power management unit as an acknowledge signal indicating completion of the power gating of the element. - View Dependent Claims (2, 3, 4, 5, 6)
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7. A power gating circuit configured to perform power gating of an element, the power gating circuit comprising:
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a first chain buffer that generates a first sleep signal by buffering an input sleep signal received from a power management unit; a first switch block that receives the first sleep signal; a second chain buffer that generates a second sleep signal by buffering the first sleep signal; and a second switch block that receive the second sleep signal, wherein the first switch block comprises; a first drive buffer configured to generate a third sleep signal by buffering the first sleep signal and a plurality of first switch cells that receives the third sleep signal, the second switch block comprises; a second drive buffer configured to generate a fourth sleep signal by buffering the second sleep signal and a plurality of second switch cells that receives the fourth sleep signal, and the second sleep signal is returned to the power management unit as an acknowledge signal indicating completion of the power gating of the element. - View Dependent Claims (8, 9, 10, 11, 12, 13, 14, 15, 16, 17)
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18. A power gating circuit configured to perform power gating of an element, the power gating circuit comprising:
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a first chain buffer that generates a first sleep signal by buffering an input sleep signal received from a power management unit; a first switch block that receives the first sleep signal; a second chain buffer that generates a second sleep signal by buffering the first sleep signal; and a second switch block that receives the second sleep signal, wherein the first switch block comprises; a first drive buffer configured to generate a third sleep signal by buffering the first sleep signal and a first plurality of first switch cells that receives the third sleep signal, and a third drive buffer configured to generate a fifth sleep signal by buffering the first sleep signal and a second plurality of first switch cells that receives the fifth sleep signal, the second switch block comprises; a second drive buffer configured to generate a second sleep signal by buffering the first sleep signal and a first plurality of second switch cells that receives the second sleep signal, and a fourth drive buffer configured to generate a sixth sleep signal by buffering the second sleep signal and a second plurality of second switch cells that receives the fifth sleep signal, and the second sleep signal is returned to the power management unit as an acknowledge signal indicating completion of the power gating of the element. - View Dependent Claims (19, 20)
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Specification