Separating Power Domains of Central Processing Units

• US 20150153821A1
• Filed: 02/10/2015
• Published: 06/04/2015
• Est. Priority Date: 06/12/2009
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Chi, Shyh-An, Lee, Jyy Anne
• Granted Patent: US 9,720,490 B2
• Time in Patent Office: Days
• US Class Current: 1/1
• CPC Class Codes: G05F 1/10 Regulating voltage or current G05F1/02 takes precedence; for electric railways B60M3/02
• CPC Class Codes: G06F 1/26 Power supply means, e.g. regulation thereof for memories G11C
• CPC Class Codes: G06F 1/28 Supervision thereof, e.g. detecting power-supply failure by out of limits supervision
• CPC Class Codes: G06F 1/3203 Power management, i.e. event-based initiation of a power-saving mode
• CPC Class Codes: G06F 1/3287 by switching off individual functional units in the computer system
• CPC Class Codes: G06F 1/3296 by lowering the supply or operating voltage
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

A circuit includes a central processing unit (CPU), which includes a first memory block having a first power domain; and a core block signally connected to the first memory block and having a second power domain disconnected from the first power domain.

Claims

1. A circuit comprising:

a processor comprising;

a first memory block having a first power domain; and

a core block coupled to the first memory block and having a second power domain; and

a logic circuit coupled to the first memory block and having a third power domain;

wherein

one or more voltage controllers controlling a first operational voltage of the first power domain and controlling a second operational voltage of the second power domain and controlling a third operational voltage of the third power domain;

the one or more voltage controllers is configured to set the second operational voltage to a first voltage level lower than the first operational voltage and the third operational voltage in a logic-circuit-focused workload mode; and

the one or more voltage controllers is configured to set the third operational voltage to a second voltage level lower than the first operational voltage and the second operational voltage in a core-block-focused workload mode.

2. The circuit of claim 1 further comprising a first voltage regulator module and a second voltage regulator module separate from the first voltage regulator module.

3. The circuit of claim 2, wherein the one or more voltage controllers are connected to, and control, each of the first voltage regulator module and the second voltage regulator module.

4. The circuit of claim 2, wherein the first voltage regulator module and the second voltage regulator module are in a same die as the processor.

5. The circuit of claim 2, wherein the one or more voltage controllers comprises:

a first dynamic voltage controller connected to, and controlling, the first voltage regulator module; and

a second dynamic voltage controller connected to, and controlling, the second voltage regulator module, wherein the first dynamic voltage controller and the second dynamic voltage controller are separated from each other.

6. The circuit of claim 2, wherein the first memory block is in a first die of a package, and wherein the core block is in a second die of the package.

7. The circuit of claim 1, wherein at least one of the first operation voltage and the second operation voltage are configured according to at least a software command received during operation of the processor.

8. A circuit comprising:

a processor comprising;

a first memory block having a first power domain and comprising a first type of memory; and

a second memory block having a second power domain separated from the first power domain, the second memory block comprising a second type of memory different from the first type of memory;

a first voltage regulator module coupled to the first memory block and configured to generate a first operation voltage for the first power domain; and

a second voltage regulator module coupled to the second memory block and configured to generate a second operation voltage for the second power domain.

9. The circuit of claim 8, wherein at least one of the first operation voltage and the second operation voltage are configured according to at least a software command received during operation of the processor.

10. The circuit of claim 8, further comprising a first voltage controller coupled to, and controlling, the first voltage regulator module to generate the first operation voltage during operation of the processor.

11. The circuit of claim 10, further comprising a second voltage controller coupled to, and controlling, the second voltage regulator module to generate the second operation voltage, wherein the first voltage controller and the second voltage controller are separated from each other.

12. The circuit of claim 8, wherein at least one of the first operation voltage and the second operation voltage are dynamically configured according to a control signal generated in response to at least a software command received during operation of the processor.

13. The circuit of claim 8, wherein each of the first voltage regulator module and the second voltage regulator module is configured to generate a plurality of positive voltages.

14. The circuit of claim 8, further comprising a first dynamic voltage controller connected to, and controlling, the first voltage regulator module to dynamically generate the first operation voltage during operation of the processor;

and

wherein the first dynamic voltage controller adopts a technology selected from the group consisting essentially of an adaptive voltage scaling (AVS) technology, a dynamic voltage and frequency scaling (DVFS) technology, and combinations thereof.

15. The circuit of claim 14 further comprising a second dynamic voltage controller connected to, and controlling, the second voltage regulator module to generate the second operation voltage, wherein the first voltage controller and the second voltage controller are separated from each other.

16. The circuit of claim 8 wherein the first voltage regulator module is configured to provide a first list of voltages and the second voltage regulator module is configured to provide a second list of voltages, one of the first list of voltages and the second list of voltages having at least one listed voltage not in the other of the first list of voltages and the second list of voltages.

17. The circuit of claim 15, the circuit further comprising:

a first dynamic voltage controller;

a first though silicon via (TSV) disposed between the first dynamic voltage controller and the first voltage regulator, the first dynamic voltage controller transmitting control signals over the first TSV to the first voltage regulator to dynamically generate the first operation voltage during operation of the processor; and

a second TSV disposed between the first voltage regulator and the first memory block, the first voltage regulator providing the first operational voltage over the second TSV to the first memory block.

18. A circuit comprising:

a processor comprising;

a first memory block having a first power domain; and

a core block coupled to the first memory block and having a second power domain; and

one or more voltage controllers controlling a first operational voltage of the first power domain and controlling a second operational voltage of the second power domain, the first operational voltage and second operational voltage controlled separately;

wherein the one or more voltage controllers is configured to set the second operational voltage from a first voltage level to a second voltage level lower than 1.0V and different from the first voltage level and the first operational voltage.

19. The circuit of claim 18, wherein the first operational voltage and second operational voltage controlled separately based on determination of an optimal first operational voltage and an optimal second operational voltage by at least the core block.

20. The circuit of claim 18, wherein the core block is operated at each of the first voltage level and second voltage level.