METHOD FOR FLIP CHIP PACKAGING CO-DESIGN
First Claim
1. A method for flip chip packaging co-design, the method comprising steps of:
- providing an Input/Output (I/O) pad information of a chip and a connection information of a PCB;
performing a first I/O pad placement according to the I/O pad information of the chip and the connection information of the PCB;
utilizing a RDL routing analysis device to perform a bump pad pitch analysis for the first I/O pad placement of the chip to generate a bump pad pitch analysis result;
performing a bump pad planning for a package according to the bump pad pitch analysis result to generate a bump pad planning result; and
performing a second I/O pad placement for the chip according to the bump pad planning result to generate an I/O pad placement result.
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Abstract
The present invention provides a method for flip chip packaging co-design. The method comprises steps of: providing an I/O pad information of a chip and a connection information of a PCB; performing a first I/O pad placement according to the I/O pad information of the chip and the connection information of the PCB; utilizing a RDL routing analysis device to perform a bump pad pitch analysis for the first I/O pad placement of the chip to generate a bump pad pitch analysis result; performing a bump pad planning for a package according to the bump pad pitch analysis result to generate a bump pad planning result; and performing a second I/O pad placement for the chip according to the bump pad planning result to generate an I/O pad placement result.
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Citations
21 Claims
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1. A method for flip chip packaging co-design, the method comprising steps of:
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providing an Input/Output (I/O) pad information of a chip and a connection information of a PCB; performing a first I/O pad placement according to the I/O pad information of the chip and the connection information of the PCB; utilizing a RDL routing analysis device to perform a bump pad pitch analysis for the first I/O pad placement of the chip to generate a bump pad pitch analysis result; performing a bump pad planning for a package according to the bump pad pitch analysis result to generate a bump pad planning result; and performing a second I/O pad placement for the chip according to the bump pad planning result to generate an I/O pad placement result. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12)
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13. A method for flip chip packaging co-design, the method comprising steps of:
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providing a power domain information of the chip, an I/O pad information of a chip, and a connection information of a PCB; performing a first I/O PAD placement according to the power domain information of the chip, the I/O pad information of the chip, and the connection information of the PCB; utilizing an IR drop analysis device to perform a bump pad count/location analysis for a plurality of power domains of the chip to generate a bump pad count/location analysis result; performing a bump pad planning for a package according to the bump pad count/location analysis result to generate a bump pad planning result; and performing a second I/O pad placement for the chip according to the bump pad planning result to generate an I/O pad placement result. - View Dependent Claims (14, 15, 16, 17, 18, 19, 20, 21)
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Specification