Self-Aligned Double Spacer Patterning Process

• US 20150155198A1
• Filed: 12/04/2013
• Published: 06/04/2015
• Est. Priority Date: 12/04/2013
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Tsai, Cheng-Hsiung, Wu, Yung-Hsu, Huang, Tsung-Min, Lee, Chung-Ju, Bao, Tien-I, Shue, Shau-Lin
• Granted Patent: US 9,123,776 B2
• Time in Patent Office: Days
• US Class Current: 1/1
• CPC Class Codes: H01L 21/0273 characterised by the treatment of photoresist layers
• CPC Class Codes: H01L 21/0332 characterised by their composition, e.g. multilayer masks, materials
• CPC Class Codes: H01L 21/0337 characterised by the process involved to create the mask, e.g. lift-off masks, sidewalls, or to modify the mask, e.g. pre-treatment, post-treatment
• CPC Class Codes: H01L 21/0338 Process specially adapted to improve the resolution of the mask
• CPC Class Codes: H01L 21/3085 characterised by their behaviour during the process, e.g. soluble masks, redeposited masks
• CPC Class Codes: H01L 21/3088 Process specially adapted to improve the resolution of the mask
• CPC Class Codes: H01L 21/31144 using masks
• CPC Class Codes: H01L 21/32133 by chemical means only
• CPC Class Codes: H01L 21/32139 using masks
• CPC Class Codes: H01L 21/76802 by forming openings in dielectrics
• CPC Class Codes: H01L 21/76816 Aspects relating to the layout of the pattern or to the size of vias or trenches layout of the interconnections per se H01L23/528; CAD of ICs G06F30/00
• CPC Class Codes: H01L 21/76877 Filling of holes, grooves or trenches, e.g. vias, with conductive material

Abstract

Embodiments of the present disclosure are a method of forming a semiconductor device and methods of patterning a semiconductor device. An embodiment is a method of forming a semiconductor device, the method including forming a first hard mask layer over a semiconductor device layer, forming a set of mandrels over the first hard mask layer, and forming a first spacer layer over the set of mandrels and the first hard mask layer. The method further includes forming a second spacer layer over the first spacer layer, patterning the first spacer layer and the second spacer layer to form a mask pattern, and patterning the first hard mask layer using the mask pattern as a mask.

Claims

1. A method of forming a semiconductor device, the method comprising:

forming a first hard mask layer over a semiconductor device layer;

forming a set of mandrels over the first hard mask layer;

forming a first spacer layer over the set of mandrels and the first hard mask layer;

forming a second spacer layer over the first spacer layer;

patterning the first spacer layer and the second spacer layer to form a mask pattern, the patterning further comprising;

etching the second spacer layer to expose the first spacer layer; and

etching the exposed first spacer layer to expose surfaces of the first hard mask layer between the set of mandrels and remaining portions of the second spacer layer; and

patterning the first hard mask layer using the mask pattern as a mask.

2. The method of claim 1, wherein the forming the first spacer layer over the set of mandrels and the first hard mask layer comprises conformally depositing the first spacer layer to have a uniform first thickness over the set of mandrels and the first hard mask layer, and wherein the forming the second spacer layer over the first spacer layer comprises conformally depositing the second spacer layer to have a uniform second thickness over the first spacer layer.

3. The method of claim 2, wherein the first thickness and the second thickness are substantially a same thickness.

4. The method of claim 1, wherein the etching the second spacer layer forms a first set of spacers having a first width on sidewalls of the set of mandrels, and wherein the etching the first spacer layer forms a second set of spacers of a second width, the second width being less than the first width.

5. The method of claim 4, wherein each of the second set of spacers adjoins two sides of a corresponding first spacer.

6. The method of claim 4, wherein each of the first set of spacers has a bottom surface adjoining a top surface of a corresponding second spacer.

7. The method of claim 1, wherein the forming the set of mandrels over the first hard mask layer comprises:

forming a mandrel layer over the first hard mask layer; and

patterning the mandrel layer to form the set of mandrels.

8. The method of claim 7, wherein the patterning the mandrel layer comprises:

forming a photoresist over the mandrel layer;

patterning the photoresist to have at least one portion of a first width;

trimming the at least one portion of the photoresist to have a second width, the second width being smaller than the first width; and

patterning the mandrel layer using the patterned and trimmed photoresist as a mask, at least one mandrel of the set of mandrels having the second width.

9. The method of claim 8, wherein the second width is about one-third of the first width.

10. The method of claim 8, wherein the photoresist is a tri-layer photoresist comprising a top photoresist layer, a middle layer, and a bottom layer, wherein the middle layer comprises an anti-reflective material, and wherein the bottom layer comprises a hard mask material.

11. The method of claim 1, wherein at least one of the first spacer layer and the second spacer layer is a metal-containing spacer layer.

12. A method of patterning a semiconductor device, the method comprising:

forming a first hard mask layer over a semiconductor device layer;

forming at least one mandrel over the first hard mask layer;

conformally depositing a first spacer layer to have a uniform thickness over the at least one mandrel and the first hard mask layer;

conformally depositing a second spacer layer to have a uniform thickness over the first spacer layer;

patterning the first spacer layer and the second spacer layer to form a first set of spacers on sidewalls of the at least one mandrel, each of the first set of spacers comprising a portion of the first spacer layer and a portion of the second spacer layer, each of the first set of spacers having a first width;

patterning the first set of spacers to form a second set of spacers over the first hard mask layer, each of the second set of spacers having a second width, the second width being less than the first width; and

patterning the first hard mask layer and the semiconductor device layer using the second set of spacers as a mask.

13. The method of claim 12, wherein the second width is about one-half of the first width.

14. The method of claim 12, wherein each of the second set of spacers are separated from adjacent spacers of the second set of spacers by a first spacing, the first spacing being substantially equal to the second width.

15. The method of claim 12, wherein at least a portion of each of the second set of spacers comprises titanium.

16. The method of claim 12, wherein the portion of the second spacer layer is over the portion of the first spacer layer in each of the first set of spacers.

17. The method of claim 12, wherein the semiconductor device layer is a low-k dielectric layer.

18. A method of patterning a semiconductor device, the method comprising:

forming a second hard mask layer over a first hard mask layer and a semiconductor device layer;

patterning the second hard mask layer to form a plurality of second hard mask portions;

conformally forming a first spacer layer over the plurality of second hard mask portions and the first hard mask layer;

conformally forming a second spacer layer over the first spacer layer;

removing top surfaces of the second spacer layer to expose top surfaces of the first spacer layer;

removing the exposed top surfaces of the first spacer layer to expose top surfaces of the first hard mask layer and to form a mask pattern, the removing of the exposed top surfaces of the first spacer layer comprising;

etching the exposed top surfaces of the first spacer layer to expose top surfaces of the second hard mask portions; and

etching remaining portions of first spacer layer to expose top surfaces of the first hard mask layer between the second hard mask portions and remaining portions of the second spacer layer; and

patterning the first hard mask layer and the semiconductor device layer using the mask pattern as a mask.

20. The method of claim 18 further comprising forming a conductive material in openings of the patterned semiconductor device layer, the conductive material forming a set of conductive lines in the patterned semiconductor device layer.

21. the method of claim 18, wherein the first spacer layer and the second spacer layer are formed to have substantially a same thickness.

19. (canceled)