STACKED BIT LINE DUAL WORD LINE NONVOLATILE MEMORY

• US 20150155236A1
• Filed: 02/10/2015
• Published: 06/04/2015
• Est. Priority Date: 08/31/2005
• Status: Active Grant

• Current Assignee: Macronix International Co., Ltd.
• Original Assignee: Macronix International Co., Ltd.
• Inventors: LUNG, HSIANG-LAN
• Granted Patent: US 9,466,566 B2
• Time in Patent Office: Days
• US Class Current: 1/1
• CPC Class Codes: H01L 21/76895 Local interconnects; Local pads, as exemplified by patent document EP0896365
• CPC Class Codes: H01L 23/50 for integrated circuit devices, e.g. power bus, number of leadsH01L23/482 - H01L23/498 take precedence
• CPC Class Codes: H01L 23/5252 comprising anti-fuses, i.e. connections having their state changed from non-conductive to conductive
• CPC Class Codes: H01L 27/0688 Integrated circuits having a three-dimensional layout
• CPC Class Codes: H01L 27/101 including resistors or capacitors only
• CPC Class Codes: H01L 27/1021 including diodes only
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
• CPC Class Codes: H10B 20/20 Programmable ROM [PROM] devices comprising field-effect components H10B20/10 takes precedence
• CPC Class Codes: H10B 99/00 Subject matter not provided for in other groups of this subclass

Abstract

An arrangement of nonvolatile memory devices, having at least one memory device level stacked level by level above a semiconductor substrate, each memory level comprising an oxide layer substantially disposed above a semiconductor substrate, a plurality of word lines substantially disposed above the oxide layer; a plurality of bit lines substantially disposed above the oxide layer; a plurality of via plugs substantially in electrical contact with the word lines and, an anti-fuse dielectric material substantially disposed on side walls beside the bit lines and substantially in contact with the plurality of bit lines side wall anti-fuse dielectrics.

Claims

1. A memory device, comprising:

a first conductive element;

a first conductive line coupled to the first conductive element, the first conductive line orthogonal to the first conductive element;

second and third conductive elements orthogonal to the first conductive element;

a first memory cell between the second and first conductive elements; and

a second memory cell between the third and first conductive elements, wherein the first memory cell is over the second memory cell.

2. The memory device of claim 1, further comprising a fourth conductive element orthogonal to and coupled to the first conductive line.

3. The memory device of claim 2, further comprising fifth and sixth conductive elements orthogonal to the fourth conductive element.

4. The memory device of claim 3, further comprising

a third memory cell between the fifth and fourth conductive elements;

and

a fourth memory cell between the sixth and fourth conductive elements, wherein the third memory cell is over the fourth memory cell.

5. The memory device of claim 4, further comprising a second conductive line parallel to the first conductive line.

6. The memory device of claim 5, further comprising a seventh conductive element orthogonal to and coupled to the second conductive line.

7. The memory device of claim 6, further comprising eighth and ninth conductive elements orthogonal to the seventh conductive element.

8. The memory device of claim 7, further comprising

a fifth memory cell between the eighth and seventh conductive elements;

and

a sixth memory cell between the ninth and seventh conductive elements, wherein the fifth memory cell is over the sixth memory cell.

9. A memory device, comprising:

first and second conductive lines;

a first conductive element orthogonal to and coupled to the first conductive line;

a second conductive element orthogonal to and coupled to the second conductive line;

a first memory cell on a first sidewall of the first conductive element;

a second memory cell on a second sidewall of the second conductive element;

a third conductive element orthogonal to the first conductive element; and

a fourth conductive element orthogonal to the second conductive element, wherein the third conductive element is over the fourth conductive element.

10. The memory device of claim 9, wherein the first memory cell is between the first conductive element and the third conductive element.

11. The memory device of claim 10, wherein the second memory cell is between the second conductive element and the fourth conductive element.

12. The memory device of claim 11, further comprising a fifth conductive element orthogonal to the first conductive element.

13. The memory device of claim 12, further comprising a sixth conductive element orthogonal the second conductive element.

14. The memory device of claim 13, further comprising a third memory cell between the fifth conductive element and the first conductive element.

15. The memory device of claim 14, further comprising a fourth memory cell between sixth conductive element and the second conductive element.

16. The memory device of claim 15, wherein the fourth memory cell is over the third memory cell.