Manufacturing a Semiconductor Device Using Electrochemical Etching, Semiconductor Device and Super Junction Semiconductor Device

• US 20150155380A1
• Filed: 12/04/2013
• Published: 06/04/2015
• Est. Priority Date: 12/04/2013
• Status: Active Grant

• Current Assignee: Infineon Technologies Austria Ag (Infineon Technologies AG)
• Original Assignee: Infineon Technologies Austria Ag (Infineon Technologies AG)
• Inventors: Schulze, Hans-Joachim, Irsigler, Peter, Weber, Hans
• Granted Patent: US 9,105,717 B2
• Time in Patent Office: Days
• US Class Current: 1/1
• CPC Class Codes: H01L 21/26513 of electrically active species
• CPC Class Codes: H01L 21/3063 Electrolytic etching
• CPC Class Codes: H01L 21/324 Thermal treatment for modifying the properties of semiconductor bodies, e.g. annealing, sintering H01L21/20 - H01L21/288 and H01L21/302 - H01L21/322 take precedence
• CPC Class Codes: H01L 29/0634 Multiple reduced surface field (multi-RESURF) structures, e.g. double RESURF, charge compensation, cool, superjunction (SJ), 3D-RESURF, composite buffer (CB) structures
• CPC Class Codes: H01L 29/0646 PN junctions
• CPC Class Codes: H01L 29/0649 Dielectric regions, e.g. SiO2 regions, air gaps
• CPC Class Codes: H01L 29/1095 Body region, i.e. base region, of DMOS transistors or IGBTs cell layout H01L29/0696
• CPC Class Codes: H01L 29/32 the imperfections being within the semiconductor body
• CPC Class Codes: H01L 29/407 Recessed field plates, e.g. trench field plates, buried field plates
• CPC Class Codes: H01L 29/41766 with at least part of the source or drain electrode having contact below the semiconductor surface, e.g. the source or drain electrode formed at least partially in a groove or with inclusions of conductor inside the semiconductor H01L29/41733 - H01L29/41758 take precedence
• CPC Class Codes: H01L 29/42356 Disposition, e.g. buried gate electrode H01L29/42324 and H01L29/4234 take precedence
• CPC Class Codes: H01L 29/42368 the thickness being non-uniform
• CPC Class Codes: H01L 29/42376 characterised by the length or the sectional shape
• CPC Class Codes: H01L 29/66272 Silicon vertical transistors H01L29/66242, H01L29/66257 and H01L29/66265 take precedence
• CPC Class Codes: H01L 29/6634 with a recess formed by etching in the source/emitter contact region H01L29/66348 takes precedence; etching of semiconductor bodies H01L21/302
• CPC Class Codes: H01L 29/66348 with a recessed gate
• CPC Class Codes: H01L 29/66727 with a step of recessing the source electrode
• CPC Class Codes: H01L 29/66734 with a step of recessing the gate electrode, e.g. to form a trench gate electrode
• CPC Class Codes: H01L 29/732 Vertical transistors
• CPC Class Codes: H01L 29/7396 with a non planar surface, e.g. with a non planar gate or with a trench or recess or pillar in the surface of the emitter, base or collector region for improving current density or short circuiting the emitter and base regions H01L29/7398 takes precedence
• CPC Class Codes: H01L 29/7397 : and a gate structure lying on a slanted or vertical surface or formed in a groove, e.g. trench gate IGBT
• CPC Class Codes: H01L 29/7811 : with an edge termination structure guard regions per se H01L29/0619; field plates per se H01L29/402
• CPC Class Codes: H01L 29/7813 : with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236

Abstract

A trench is formed in a semiconductor substrate between mesas of a first conductivity type. The trench extends from a process surface down to a bottom plane. A semiconductor layer of a second, complementary conductivity type is formed on sidewalls of the trench. At least in the mesas a vertical impurity concentration profile vertical to the process surface is non-constant between the process surface and the bottom plane. A portion of the semiconductor layer in the trench is removed by electrochemical etching. Thereafter, the thickness of the recessed semiconductor layer images the vertical impurity concentration profile in the mesa.

Claims

1. A method of manufacturing a semiconductor device, the method comprising:

forming a trench in a semiconductor substrate between mesas of a first conductivity type, the trench extending from a process surface down to a bottom plane;

forming a semiconductor layer of a second, complementary conductivity type on sidewalls of the trench, wherein at least in the mesas a vertical impurity concentration profile vertical to the process surface is non-constant between the process surface and the bottom plane; and

thereafter

removing a portion of the semiconductor layer in the trench by electrochemical etching.

2. The method of claim 1, further comprising:

implanting impurities into at least one of the semiconductor substrate and the semiconductor layer before the electrochemical etching to define the non-constant vertical impurity concentration profile.

3. The method of claim 1, further comprising:

implanting protons into at least one of the semiconductor substrate and the semiconductor layer; and

electrically activating the implanted protons as donors by thermal processing before the electrochemical etching to define the non-constant vertical impurity concentration profile.

4. The method of claim 3, further comprising:

thermal processing the semiconductor substrate and the semiconductor layer after the electrochemical etching to deactivate the proton-induced donors as donors.

5. The method of claim 3, wherein

implanting protons comprises a plurality of implant processes at different implant energies.

6. The method of claim 5, wherein

the implant processes are carried out at different implant doses.

7. The method of claim 1, wherein

between the process surface and the bottom plane a maximum net impurity concentration exceeds at least two times a minimum net impurity concentration.

8. The method of claim 1, further comprising:

filling the trench with at least one of an intrinsic or a lightly doped semiconductor material, a dielectric material and a passivation material.

9. The method of claim 1, further comprising:

closing the trench with an epitaxial layer grown by epitaxy.

10. The method of claim 1, wherein

the electrochemical etching comprises bringing an etching solution into contact with the semiconductor layer while applying a blocking voltage between the etching solution and the semiconductor substrate.

11. The method of claim 10, further comprising:

introducing impurities of the second conductivity type before the electrochemical etching to form a heavily doped region of the second conductivity type in the semiconductor layer or the semiconductor substrate outside the trench, wherein the etching solution is in direct contact with the heavily doped region during the electrochemical etching.

12. A semiconductor device, comprising:

semiconductor mesas of a first conductivity type extending between a first surface and a bottom plane of a semiconductor portion; and

a semiconductor structure of a second, complementary conductivity type extending along sidewalls of the semiconductor mesas,

wherein a thickness of the semiconductor structure has a local maximum value at a first distance to both the first surface and the bottom plane, and a vertical impurity concentration profile in the semiconductor portion has a local maximum at the first distance to the first surface.

13. The semiconductor device of claim 12, wherein

the thickness of the semiconductor structure has more than one local maximum along the respective sidewall of the semiconductor mesas.

14. The semiconductor device of claim 12, wherein

two semiconductor structures extend on opposite sidewalls of neighboring semiconductor mesas.

15. The semiconductor device of claim 12, wherein

the sidewalls of the semiconductor mesas are vertical to the first surface.

16. (canceled)

17. A super junction semiconductor device, comprising:

a semiconductor portion comprising a subsurface structure extending from a first surface of the semiconductor portion between mesas down to a bottom plane,

wherein the mesas have a first conductivity type and the subsurface structure comprises semiconductor structures of a second, complementary conductivity type extending along sidewalls of the mesas,

wherein a thickness of the semiconductor structures has a local maximum at a first distance to the first surface, the first distance being smaller than a main distance between the first surface and the bottom plane, and

wherein the super junction semiconductor device is a vertical insulated gate field effect transistor including a first load electrode and a control terminal at a first side of the semiconductor portion and a second load electrode at a second side of the semiconductor portion opposite to the first side.

18. The super junction semiconductor device of claim 17,

wherein the subsurface structure includes a fill structure of a filling material separating the semiconductor structures of the subsurface structure, the filling material being at least one of an intrinsic and a lightly doped semiconductor material and a dielectric material.

19. The super junction semiconductor device of claim 17, wherein the subsurface structure comprises a void.

20. (canceled)