RF AMPLIFIER OPERATIONAL IN DIFFERENT POWER MODES

• US 20150155831A1
• Filed: 12/02/2014
• Published: 06/04/2015
• Est. Priority Date: 12/02/2013
• Status: Active Grant

• Current Assignee: Qorvo US, Inc. (Qorvo, Inc.)
• Original Assignee: RF Micro Devices Incorporated (Qorvo, Inc.)
• Inventors: Shirvani, Alireza
• Granted Patent: US 9,935,585 B2
• Time in Patent Office: Days
• US Class Current: 1/1
• CPC Class Codes: H03F 1/0211 with control of the supply voltage or current
• CPC Class Codes: H03F 1/0261 with control of the polarisation voltage or current, e.g. gliding Class A
• CPC Class Codes: H03F 1/22 by use of cascode coupling, i.e. earthed cathode or emitter stage followed by earthed grid or base stage respectively
• CPC Class Codes: H03F 1/223 with MOSFET's
• CPC Class Codes: H03F 2200/222 A circuit being added at the input of an amplifier to adapt the input impedance of the amplifier
• CPC Class Codes: H03F 2200/294 the amplifier being a low noise amplifier [LNA]
• CPC Class Codes: H03F 2200/387 A circuit being added at the output of an amplifier to adapt the output impedance of the amplifier
• CPC Class Codes: H03F 2200/451 the amplifier being a radio frequency amplifier
• CPC Class Codes: H03F 2200/61 the cascode amplifier has more than one common gate stage
• CPC Class Codes: H03F 3/193 with field-effect devices H03F3/195 takes precedence
• CPC Class Codes: H03F 3/211 using a combination of several amplifiers H03F3/60 takes precedence

Abstract

Embodiments of a radio frequency (RF) amplification are disclosed. The RF amplification device includes a first RF amplification circuit, a second RF amplification circuit, and power control circuitry operable in a first power mode and a second power mode. The first RF amplification circuit has a cascode amplifier stage configured to amplify an RF signal. The cascode amplifier stage has an input transistor and a cascode output transistor that are stacked in cascode. The second RF amplification circuit is configured to amplify the RF signal. The power control circuitry is configured to bias the first cascode output transistor so that the first cascode output transistor operates in a saturation region in the first power mode and bias the first cascode output transistor so that the first cascode output transistor operates in a triode region in the second power mode. The second RF amplification circuit is assisted without introducing additional loading.

Claims

1. A radio frequency (RF) amplification device comprising:

a first RF amplification circuit comprising a cascode amplifier stage configured to amplify an RF signal, wherein the cascode amplifier stage has a first input transistor and a first cascode output transistor that are stacked in cascode;

a second RF amplification circuit configured to amplify the RF signal, wherein the second RF amplification circuit is coupled to the cascode amplifier stage between the first input transistor and the first cascode output transistor;

power control circuitry operable in a first power mode and a second power mode, wherein the power control circuitry is configured to;

bias the first cascode output transistor so that the first cascode output transistor operates in a saturation region in the first power mode;

bias the first cascode output transistor so that the first cascode output transistor operates in a triode region in the second power mode.

2. The RF amplification device of claim 1 wherein the power control circuitry is further configured to:

bias the first RF amplification circuit so that the first RF amplification circuit is activated in the first power mode, wherein biasing the first RF amplification circuit so that the first RF amplification circuit is activated comprises biasing the first cascode output transistor so that the first cascode output transistor operates in the saturation region;

bias the second RF amplification circuit so that the second RF amplification circuit is activated in the second power mode.

3. The RF amplification device of claim 2 wherein:

the first RF amplification circuit is configured to operate at higher power levels than the second RF amplification circuit such that the first power mode is a higher power mode than the second power mode.

4. The RF amplification device of claim 2 wherein:

the first RF amplification circuit is a high power RF amplification circuit;

the second RF amplification circuit is a medium power RF amplification circuit; and

the power control circuitry is configured such that the first power mode is a high power mode and the second power mode is a medium power mode.

5. The RF amplification device of claim 2 wherein the power control circuitry is further configured to:

bias the first RF amplification circuit so that the first RF amplification circuit is deactivated in the second power mode;

bias the second RF amplification circuit so that the second RF amplification circuit is deactivated in the first power mode.

6. The RF amplification device of claim 5 wherein the power control circuitry is further configured to bias the cascode amplifier stage so that the first input transistor is turned off in the second power mode.

7. The RF amplification device of claim 1 wherein the cascode amplifier stage further comprises a first cascode intermediary transistor stacked between the first input transistor and the first cascode output transistor and wherein the power control circuitry is further configured to:

bias the first cascode intermediary transistor such that the first cascode intermediary transistor operates in the saturation region in the first power mode;

bias the first cascode intermediary transistor so that the first cascode intermediary transistor is turned off in the second power mode.

8. The RF amplification device of claim 7 wherein:

the second RF amplification circuit is coupled to the cascode amplifier stage between the first cascode intermediary transistor and the first cascode output transistor.

9. The RF amplification device of claim 8 further comprising a matching network coupled to the second RF amplification circuit and connected to the cascode amplifier stage between the first cascode intermediary transistor and the first cascode output transistor such that an output impedance of the second RF amplification circuit is and a cascode amplifier input impedance is presented to the matching network, wherein the matching network is configured to substantially match the output impedance of the second RF amplification circuit to the cascode amplifier input impedance while the power control circuitry is in the second power mode.

10. The RF amplification device of claim 1 wherein the first RF amplification circuit further comprises a plurality of amplifier stages coupled in cascade, wherein the plurality of amplifier stages includes the cascode amplifier stage.

11. The RF amplification device of claim 10 wherein:

the cascode amplifier stage is a final amplifier stage of the first RF amplification circuit; and

the plurality of amplifier stages includes a driver amplifier stage coupled in cascade with the final amplifier stage.

12. The RF amplification device of claim 1 further comprising an input matching network operable to input the RF signal such that a source impedance is presented to the input matching network wherein:

the first RF amplification circuit is connected to the input matching network such that a first input impedance of the first RF amplification circuit is presented to the input matching network;

the second RF amplification circuit is connected to the input matching network such that a second input impedance of the second RF amplification circuit is presented to the input matching network; and

the input matching network is configured to substantially match the source impedance and the first input impedance as presented when the power control circuitry is in the first power mode and to substantially match the source impedance and the second input impedance as presented when the power control circuitry is in the second power mode.

13. The RF amplification device of claim 1 wherein:

the first RF amplification circuit is provided in a first signal path;

the second RF amplification circuit is provided in a second signal path;

the second signal path is connected to the cascode amplifier stage between the first input transistor and the first cascode output transistor.

14. The RF amplification device of claim 13 further comprising an output matching network operable to output the RF signal such that a load impedance is presented to the output matching network, wherein the output matching network is provided in the first signal path so as to receive the RF signal from the first cascode output transistor.

15. The RF amplification device of claim 13 further comprising an intermediary matching network provided in the second signal path between the second RF amplification circuit and the cascode amplifier stage.

16. The RF amplification device of claim 13 further comprising a switch device operable to be opened and operable to be closed, wherein the switch device is coupled in shunt to the second signal path and wherein the power control circuitry is further configured to:

operate the switch device in the first power mode so that the switch device is open;

operate the switch device in the second power mode so that the switch device is closed.

17. The RF amplification device of claim 16 further comprising an intermediary matching network provided in the second signal path between the second RF amplification circuit and the cascode amplifier stage wherein the switch device is connected in shunt to the second signal path between the second RF amplification circuit and to the intermediary matching network.

18. The RF amplification device of claim 1 wherein the second RF amplification circuit comprises a push pull amplifier stage having a first push transistor and a first pull transistor, wherein the power control circuitry is further configured to:

bias the first pull transistor so that the first push transistor is turned off in the first power mode; and

bias the first push transistor so that the first pull transistor operates in a triode region in the first power mode.

19. The RF amplification device of claim 18 further comprising a matching network coupled to the push pull amplifier stage between the first pull transistor and the first push transistor and coupled to the cascode amplifier stage between the first input transistor and the first cascode output transistor, wherein the matching network comprises:

a first inductor wherein the first inductor coupled to the second RF amplification circuit and coupled to the cascode amplifier stage between the first cascode output transistor and the first input transistor; and

a first capacitor connected in series with the first inductor;

a second capacitor coupled in shunt to the second RF amplification circuit.

20. The RF amplification device of claim 1 wherein comprises a charge pump, and the first cascode output transistor includes a control contact and a supply contact wherein the power control circuitry is configured to bias the first cascode output transistor in the second power mode so that the first cascode output transistor operates in the triode region by being configured to:

generate a supply voltage from a power source voltage, wherein the supply contact of the first cascode output transistor is connected to be biased by the supply voltage;

generate a transistor control voltage greater than the power source voltage with the charge pump, wherein the control contact of the first cascode output transistor is connected to be biased by the transistor control voltage.

21. The RF amplification device of claim 1 further comprising a matching network coupled to the second RF amplification circuit and to the cascode amplifier stage between the first input transistor and the first cascode output transistor, wherein the matching network comprises:

a first inductor wherein the first inductor coupled to the second RF amplification circuit and coupled to the cascode amplifier stage between the first cascode output transistor and the first input transistor;

a first capacitor connected in series with the first inductor;

a second capacitor coupled in shunt to the second RF amplification circuit;

a switch device coupled in shunt to an intermediate tap of the first inductor.

22. The RF amplification device of claim 21 wherein the power control circuitry is further configured to:

operate the switch device in the first power mode so that the switch device is open; and

operate the switch device in the second power mode so that the switch device is closed.

23. The RF amplification device of claim 1 wherein the second RF amplification circuit comprises a first push pull amplifier stage having a first push transistor, a first pull transistor, a second cascode output transistor, and a third cascode output transistor, wherein:

the first push transistor and the second cascode output transistor are stacked in cascode;

the first pull transistor and the third cascode output transistor are stacked in cascode; and

the second cascode output transistor and the third cascode output transistor are stacked in cascode.

24. The RF amplification device of claim 23 wherein the power control circuitry is configured to:

bias the first pull transistor so that the first push transistor is turned off in the first power mode;

bias the third cascode output transistor so that the first pull transistor is turned off in the first power mode;

bias the first push transistor so that the first push transistor operates in a triode region in the first power mode;

bias the second cascode output transistor so that the second cascode output transistor operates in a triode region in the first power mode.

25. The RF amplification device of claim 24 wherein the power control circuitry is configured to:

bias the first push transistor so that the first push transistor operates in a saturation region in the second power mode;

bias the second cascode output transistor so that the second cascode output transistor operates in a saturation region in the second power mode;

bias the first pull transistor so that the first pull transistor operates in a saturation region in the second power mode;

bias the third cascode output transistor so that the third cascode output transistor operates in a saturation region in the second power mode.

26. The RF amplification device of claim 23 wherein the second RF amplification circuit further comprises a driver amplifier stage and wherein the first push pull amplifier stage is a final amplifier stage of the second RF amplification circuit.

27. The RF amplification device of claim 26 wherein the driver amplifier stage is a second push pull amplifier stage having a second push transistor, a second pull transistor, a fourth cascode output transistor, and a fifth cascode output transistor, wherein:

the second push transistor and the fourth cascode output transistor are stacked in cascode;

the second pull transistor and the fifth cascode output transistor are stacked in cascode; and

the fourth cascode output transistor and the fifth cascode output transistor are stacked in cascode.

28. The RF amplification device of claim 1 comprising the second RF amplification circuit comprises a feedback circuit configured to maintain an input impedance of the second RF amplification circuit at approximately a characteristic impedance.

29. A method of amplifying a radio frequency (RF) signal comprising:

amplifying an RF signal with a first RF amplification circuit during a first power mode that includes a cascode amplifier stage having a first input transistor and a first cascode output transistor that are stacked in cascode;

biasing the first cascode output transistor so that the first cascode output transistor operates in a saturation region in the first power mode;

amplifying the RF signal with a second RF amplification circuit during a second power mode, wherein the second RF amplification circuit is coupled to the cascode amplifier stage between the first input transistor and the first cascode output transistor;

biasing the first cascode output transistor in the second power mode so that the first cascode output transistor operates in a triode region.

30. The method of claim 29 further comprising:

biasing the first RF amplification circuit so that the first RF amplification circuit is deactivated in the second power mode; and

biasing the second RF amplification circuit so that the second RF amplification circuit is deactivated in the first power mode.