VOLTAGE DROOP MITIGATION IN 3D CHIP SYSTEM

• US 20150160975A1
• Filed: 12/31/2013
• Published: 06/11/2015
• Est. Priority Date: 12/09/2013
• Status: Active Grant

• Current Assignee: Advanced Micro Devices, Inc.
• Original Assignee: Advanced Micro Devices, Inc.
• Inventors: Xie, Yuan, Xu, Yi, Hu, Xing
• Granted Patent: US 9,595,508 B2
• Time in Patent Office: Days
• US Class Current: 1/1
• CPC Class Codes: G06F 1/329 by task scheduling
• CPC Class Codes: G06F 2119/06 Power analysis or power optimisation
• CPC Class Codes: G06F 2119/12 Timing analysis or timing optimisation
• CPC Class Codes: G06F 30/30 Circuit design
• CPC Class Codes: G06F 30/3312 Timing analysis
• CPC Class Codes: G06F 9/4881 Scheduling strategies for dispatcher, e.g. round robin, multi-level priority queues
• CPC Class Codes: H01L 2224/16145 the bodies being stacked
• CPC Class Codes: H01L 2224/16225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/73253 Bump and layer connectors
• CPC Class Codes: H01L 2225/06513 Bump or bump-like direct electrical connections between devices, e.g. flip-chip connection, solder bumps
• CPC Class Codes: H01L 2225/06517 Bump or bump-like direct electrical connections from device to substrate
• CPC Class Codes: H01L 2225/06541 Conductive via connections through the device, e.g. vertical interconnects, through silicon via [TSV]
• CPC Class Codes: H01L 2225/06589 Thermal management, e.g. cooling
• CPC Class Codes: H01L 23/5286 Arrangements of power or ground buses
• CPC Class Codes: H01L 25/0657 Stacked arrangements of devices
• CPC Class Codes: H01L 25/074 Stacked arrangements of non-apertured devices
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
• CPC Class Codes: H01L 2924/15311 being a ball array, e.g. BGA
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

The present invention relates to a multichip system and a method for scheduling threads in 3D stacked chip. The multichip system comprises a plurality of dies stacked vertically and electrically coupled together; each of the plurality of dies comprising one or more cores, each of the plurality of dies further comprising: at least one voltage violation sensing unit, the at least one voltage violation sensing unit being connected with the one or more cores of each die, the at least one voltage sensing unit being configured to independently sense voltage violation in each core of each die; and at least one frequency tuning unit, the at least one frequency tuning unit being configured to tune the frequency of each core of each die, the at least one frequency tuning unit being connected with the at least one voltage violation sensing unit. The multichip system and method described in present invention have many advantages, such as reducing voltage violation, mitigating voltage droop and saving power.

Claims

1. A multichip system comprising a plurality of dies stacked vertically and electrically coupled together;

each of the plurality of dies comprising one or more cores, each of the plurality of dies further comprising;

at least one voltage violation sensing unit, the at least one voltage violation sensing unit being connected with the one or more cores of each die, the at least one voltage violation sensing unit being configured to independently sense voltage violation in each core of each die; and

at least one frequency tuning unit, the at least one frequency tuning unit being configured to tune the frequency of each core of each die, the at least one frequency tuning unit being connected with the at least one voltage violation sensing unit.

2. The multichip system of claim 1, wherein the at least one voltage violation sensing unit is a critical-path monitor.

3. The multichip system of claim 2, wherein the at least one frequency tuning unit is a digital-phase locked loop.

4. The multichip system of claim 1, wherein the multichip system further comprises a performance monitor and a voltage regulator, the performance monitor being connected with one or more of the frequency tuning units and being configured to supervise the frequency of the stacked dies, and the voltage regulator being connected with the performance monitor and being configured to regulate the voltage supplied to the plurality of dies.

5. The multichip system of claim 3, wherein the multichip system further comprises a performance monitor and a voltage regulator, the performance monitor being connected with one or more of the frequency tuning units and being configured to supervise the frequency of the stacked dies, and the voltage regulator being connected with the performance monitor and being configured to regulate the voltage supplied to the plurality of dies.

6. A control method for a 3D stacked chip system, the 3D stacked chip system comprising a plurality of dies stacked vertically, each of the plurality of dies comprising one or more cores, the method comprising:

(a) sensing whether there is voltage violation in the one or more cores of a die by means of at least one voltage violation sensing unit connected with the core;

(b) if yes, tuning the frequency of the die by means of a frequency tuning unit connected with the voltage violation sensing unit; and

(c) if no, continuing the step (a),

wherein the control method is performed independently for each die in the 3D stacked chip.

7. The control method for 3D stacked chip system of claim 6, further comprising:

monitoring the frequency of the 3D stacked chip for determining whether the frequency exceeds an upper threshold or is lower than a lower bound,

if the frequency exceeds the upper threshold, reducing a voltage supplied to the 3D stacked chip;

if the frequency is lower than the lower bound, raising the voltage supplied to the 3D stacked chip.

8. The control method for 3D stacked chip system of claim 6, wherein the voltage violation sensing unit is a critical-path monitor.

9. The control method for 3D stacked chip system of claim 7, wherein the voltage violation sensing unit is a critical-path monitor.

10. The control method for 3D stacked chip system of claim 8, wherein the frequency tuning unit is a digital-phase locked loop.

11. A method for scheduling threads in a 3D stacked chip system, the method comprising the steps of:

(a) estimating intrinsic droop intensity of a plurality of threads from one or more applications;

(b) sorting the threads in descending order in terms of the intrinsic droop intensity and enqueuing them into a queue;

(c) selecting the thread at the head of the queue and placing it in an available core of the bottommost available die of the 3D stacked chip; and

(d) checking if the queue is empty, and repeating step (c) until the queue is empty.

12. The method of claim 11, wherein if multiple threads are estimated to have the same intrinsic droop intensity, employing a round-robin algorithm to choose threads from different applications to alleviate interference in horizontal direction.

13. The method of claim 11, further comprising departing a voltage-violent thread executed in a core of the 3D stacked chip and the cache bank in the 3D stacked chip through migrating data in the cache bank to a remote cache bank or allocating a voltage-mild thread to the core to avoid core-cache resonance when a cache behavior monitoring indicates a core-cache resonance occurs.

14. The method of claim 12, further comprising departing a voltage-violent thread executed in a core of the 3D stacked chip and the cache bank in the 3D stacked chip through migrating data in the cache bank to a remote cache bank or allocating a voltage-mild thread to the core to avoid core-cache resonance when a cache behavior monitoring indicates a core-cache resonance occurs.

15. A system for scheduling threads in a 3D stacked chip system, comprising:

means for estimating intrinsic droop intensity of a plurality of threads from one or more applications;

means for sorting the threads in descending order in terms of the intrinsic droop intensity and enqueuing them into a queue;

means for selecting the thread at the head of the queue and placing it in available core of the bottommost available die; and

means for checking if the queue is empty.

16. The system of claim 15, further comprising:

means for employing a round-robin algorithm to choose threads from different applications to alleviate interference in horizontal direction.

17. The system of claim 15, further comprising:

means for departing a voltage-violent thread executed in a core of the 3D stacked chip and the cache bank in the 3D stacked chip through migrating data in the cache bank to a remote cache bank or allocating a voltage-mild thread to the core to avoid core-cache resonance when a cache behavior monitoring indicates a core-cache resonance occurs.

18. The system of claim 16, further comprising:

means for departing a voltage-violent thread executed in a core of the 3D stacked chip and the cache bank in the 3D stacked chip through migrating data in the cache bank to a remote cache bank or allocating a voltage-mild thread to the core to avoid core-cache resonance when a cache behavior monitoring indicates a core-cache resonance occurs.