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VOLTAGE DROOP MITIGATION IN 3D CHIP SYSTEM

  • US 20150160975A1
  • Filed: 12/31/2013
  • Published: 06/11/2015
  • Est. Priority Date: 12/09/2013
  • Status: Active Grant
First Claim
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1. A multichip system comprising a plurality of dies stacked vertically and electrically coupled together;

  • each of the plurality of dies comprising one or more cores, each of the plurality of dies further comprising;

    at least one voltage violation sensing unit, the at least one voltage violation sensing unit being connected with the one or more cores of each die, the at least one voltage violation sensing unit being configured to independently sense voltage violation in each core of each die; and

    at least one frequency tuning unit, the at least one frequency tuning unit being configured to tune the frequency of each core of each die, the at least one frequency tuning unit being connected with the at least one voltage violation sensing unit.

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