ADDRESS STORAGE CIRCUIT AND MEMORY AND MEMORY SYSTEM INCLUDING THE SAME

• US 20150162071A1
• Filed: 02/06/2015
• Published: 06/11/2015
• Est. Priority Date: 12/11/2013
• Status: Active Grant

• Current Assignee: SK Hynix Inc.
• Original Assignee: SK Hynix Inc.
• Inventors: YOON, Seok-Cheol, KIM, Bo-Yeun, KIM, Jae-Il, JANG, Kyoung-Chul
• Granted Patent: US 9,734,888 B2
• Time in Patent Office: Days
• US Class Current: 1/1
• CPC Class Codes: G11C 11/406 Management or control of the refreshing or charge-regeneration cycles
• CPC Class Codes: G11C 11/4085 Word line control circuits, e.g. word line drivers, - boosters, - pull-up, - pull-down, - precharge
• CPC Class Codes: G11C 7/02 with means for avoiding parasitic signals

Abstract

A memory including a plurality of word lines to which one or more memory cells are coupled, an address storage unit suitable for storing an input address corresponding to a first external signal that is inputted at a random time, and a control unit suitable for activating a word line corresponding to the input address of the plurality of word lines in response to an active command and refreshing one or more target word lines selected using an address stored in the address storage unit when performing a refresh operation.

Claims

1. A memory, comprising:

a plurality of word lines wherein one or more memory cells are coupled to individual word lines;

an address storage unit suitable for storing an input address corresponding to a first external signal that is received at a random time; and

a control unit suitable for activating a word line corresponding to the input address of the plurality of word lines in response to an active command and refreshing one or more target word lines selected using an address stored in the address storage unit when performing a refresh operation.

2. The memory of claim 1, wherein the one or more target word lines comprise one or more word lines corresponding to the address stored in the address storage unit and one or more word lines adjacent to the word line corresponding to the address stored in the address storage unit.

3. The memory of claim 1, wherein:

the first external signal is the active command; and

the address storage unit determines a time at which the input address is stored using a period signal that oscillates in a set cycle and a second external signal that is externally received.

4. The memory of claim 3, wherein the address storage unit comprises:

an enable signal generation unit suitable for activating an enable signal when the second external signal is received by a first set number of times or more in a state in which the period signal is a first level, and deactivating the enable signal when the second external signal is received by a second set number of times or more in a state in which the period signal is a second level; and

a storage unit suitable for storing the input address when the active command is received if the enable signal is activated.

5. The memory of claim 3, wherein the second external signal comprises one or more of the active command, a precharge command, a write command, a read command, a refresh command, the input address, and data.

6. The memory of claim 1, wherein:

the first external signal is the active command; and

the address storage unit determines a time at which the input address is stored, using first and second counting signals,

wherein the first and second counting signals comprise one or more of the active command, a precharge command, a write command, a read command, a refresh command, the input address, data, and a period signal oscillating in a set cycle.

7. The memory of claim 6, wherein the address storage unit comprises:

a first counting information generation unit suitable for generating a first counting information by counting the first counting signal;

a second counting information generation unit suitable for generating a second counting information by counting the second counting signal; and

a storage unit suitable for storing the input address when the active command is received if the first counting information and the second counting information have corresponding values.

8. The memory of claim 6, wherein the first counting information has an offset value or includes a plurality of bits, a part of which is fixed, and the second counting information is reset to an initial value when the input address is stored.

9. The memory of claim 6, further comprising:

an address counting unit suitable for generating a counting address varied in response to the refresh command,

wherein the address storage unit generates a counting information in response to the active command and stores the input address when the active command is received if the counting address and the counting information have corresponding values; and

the control unit refreshes a word line corresponding to the counting address in response to the refresh command.

10. The memory of claim 1, wherein the first external signal is the active command, and the address storage unit comprises:

a random number generation unit suitable for generating a random number in response to the active command; and

a storage unit suitable for storing the input address in response to the active command if the random number generated from the random number generation unit is identical with a set value.

11. The memory of claim 1, wherein the control unit generates addresses of one or more word lines adjacent to a word line corresponding to the address stored in the address storage unit.

12. The memory of claim 1, wherein the control unit sequentially refreshes the plurality of word lines in response to a refresh command that is periodically received, but refreshes the one or more target word lines when the refresh command is received a set number of times.

13. The memory of claim 1, wherein the control unit sequentially refreshes the plurality of word lines in response to a refresh command that is periodically received, but refreshes the one or more target word lines when the refresh command is received after the input address is stored in the address storage unit.

14. The memory of claim 1, wherein the control unit sequentially refreshes the plurality of word lines in response to a refresh command that is periodically received, but refreshes the one or more target word lines when a target refresh command is received.

15. An address storage circuit for storing an address inputted to a memory, comprising:

a period signal generation unit suitable for generating a period signal that oscillates in a set cycle;

an enable signal generation unit suitable for activating an enable signal, when an external signal is received from an outside of the memory by a first set number of times or more in a state in which the period signal is a first level, and deactivating the enable signal, when the external signal is received by a second set number of times or more in a state in which the period signal is a second level; and

a storage unit suitable for storing an address corresponding to an active command when the active command is inputted to the memory in a state in which the enable signal is activated.

16. The address storage circuit of claim 15, wherein the external signal comprises one or more of the active command, a precharge command, a write command, a read command, a refresh command, the address, and data.

17. The address storage circuit of claim 15, wherein the period signal generation unit comprises an oscillator.

18. The address storage circuit of claim 15, wherein the enable signal generation unit comprises:

a first signal generation unit suitable for generating a pre-enable signal in response to the period signal and the external signal; and

a second signal generation unit suitable for generating the enable signal by shifting the pre-enable signal in response to the external signal.

19. An address storage circuit for storing an address inputted to a memory, comprising:

a first counting information generation unit suitable for generating a first counting information by performing a counting operation in response to a first counting signal;

a second counting information generation unit suitable for generating a second counting information by performing a counting operation in response to a second counting signal; and

a storage unit suitable for storing an address corresponding to an active command when the active command is received if the first counting information and the second counting information have corresponding values,

wherein each of the first counting signal and the second counting signal comprise one or more of the active command, a precharge command, a write command, a read command, a refresh command, an address, data, and a period signal that oscillates in a set cycle.

20. The address storage circuit of claim 19, wherein the first counting information generation unit makes the first counting information have an offset value or makes a part of a plurality of bits of the first counting information have a fixed value.

21. The address storage circuit of claim 19, wherein:

the first counting information generation unit resets the first counting information to an initial value when the first counting information has a set value; and

the second counting information generation unit resets the second counting information to an initial value when the input address is stored.

22. The address storage circuit of claim 19, wherein:

the first counting signal is the refresh command; and

the second counting signal is the active command.

23. A memory system, comprising:

a memory having a plurality of word lines to which one or more memory cells are coupled and an address storage unit for storing an input address corresponding to an active command at a random time and suitable for activating a word line corresponding to the input address of the plurality of word lines in response to the active command and refreshing one or more target word lines selected using an address stored in the address storage unit when performing a refresh operation; and

a memory controller suitable for applying a plurality of control signals for controlling an operation of the memory, the control signals comprising the active command, a precharge command, a write command, a read command, a refresh command, the input address, and data.

24. The memory system of claim 23, wherein the address storage unit determines a point of time, at which the input address is stored, using one or more of a period signal that oscillates in a set cycle and the plurality of control signals received from the memory controller.

25. The memory system of claim 23, wherein the address storage unit stores the input address when the active command is received if a first counting information and a second counting information have corresponding values,

wherein the first counting information corresponding to a result of a counting operation performed in response to a first counting signal, comprising one or more of the plurality of control signals and a first period signal that oscillates in a first set cycle, and

wherein the second counting information corresponding to a result of a counting operation performed in response to a second counting signal, comprising one or more of the plurality of control signals and a second period signal that oscillates in a second set cycle.

26. The memory system of claim 23, wherein the memory sequentially refreshes the plurality of word lines in response to the refresh command that is periodically received, but refreshes the one or more target word lines when the refresh command is received by a set number of times.

27. The memory system of claim 23, wherein the memory sequentially refreshes the plurality of word lines in response to the refresh command that is periodically received, but refreshes the one or more target word lines when the refresh command is received after the address is stored in the address storage unit.

28. The memory system of claim 23, wherein:

the memory controller inputs a target refresh command to the memory; and

the memory sequentially refreshes the plurality of word lines in response to the refresh command that is periodically received, but refreshes the one or more target word lines in response to the target refresh command.

29. The memory system of claim 23, wherein the one or more target word lines comprise one or more word lines corresponding to the address stored in the address storage unit and one or more word lines adjacent to the word line corresponding to the address stored in the address storage unit.

30. A memory comprising:

a plurality of word lines;

an address storage unit suitable for storing addresses of word lines activated at first and second sections which are alternately repeated, storing an address which is stored last in the first section as a first address when the second section is started, and updating the first address into an address of a currently activated word line at each active operation in the second section; and

a control unit suitable for sequentially refreshing the plurality of word lines during a refresh operation, and refreshing one or more target word lines adjacent to a word line corresponding to the first address during a target refresh operation.

31. The memory of claim 30, wherein a period signal is at a first level during the first section, and the period signal is at a second level during the second section.

32. The memory of claim 31, wherein the address storage unit comprises a period signal generation unit suitable for generating the period signal.

33. The memory of claim 30, wherein the address storage unit comprises:

a first storage unit suitable for storing an address of a word line activated at the first and second sections, and updating the stored address into the address of the currently activated word line at each active operation; and

a second storage unit suitable for storing the address of the first storage unit as the first address at the second section.

34. The memory of claim 33, wherein the second storage unit updates the first address into the address of the first storage unit whenever the address of the first storage unit is updated at the second section.

35. The memory of claim 30, wherein the control unit generates one or more second addresses corresponding to the one or more target word lines using the first address.

36. The memory of claim 35, wherein the control unit generates the one or more second addresses by adding or subtracting a predetermined value from the first address.

37. The memory of claim 30, wherein the control unit performs the refresh operation in response to a refresh command which is periodically inputted, and performs the target refresh operation when the refresh command is inputted a predetermined number of times.

38. The memory of claim 30, wherein the control unit performs the refresh operation in response to a refresh command which is periodically inputted, and performs the target refresh operation when a target refresh command is inputted.