ARCHITECTURE FOR 3-D NAND MEMORY

• US 20150162084A1
• Filed: 02/19/2015
• Published: 06/11/2015
• Est. Priority Date: 06/15/2012
• Status: Active Grant

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: Morooka, Midori, Tanaka, Tomoharu
• Granted Patent: US 10,269,429 B2
• Time in Patent Office: Days
• US Class Current: 1/1
• CPC Class Codes: G11C 16/0483 comprising cells having several storage transistors connected in series
• CPC Class Codes: G11C 16/06 Auxiliary circuits, e.g. for writing into memory
• CPC Class Codes: G11C 16/3427 Circuits or methods to prevent or reduce disturbance of the state of a memory cell when neighbouring cells are read or written
• CPC Class Codes: G11C 2213/71 Three dimensional array

Abstract

Apparatuses are described that include stacked arrays of memory cell strings and their methods of operation. Apparatuses include architectures that reduce the use of several common components, allowing greater device density and smaller device size for a given semiconductor area.

Claims

1. An apparatus, comprising:

a plurality of stacked memory arrays, including a first array of memory cell strings and a second array of memory cell strings stacked on top of the first array;

data plates associated with multiple rows of memory cell strings in at least one of the plurality of stacked memory arrays; and

for each of the memory cell strings associated with a respective one of the data plates, a plurality of select gates coupled between a memory cell region of the memory cell string and the respective one of the data plates,

wherein the respective one of the data plates is shared by some of the memory cell strings in the first array and the second array, and wherein the respective one of the data plates is coupled to two adjacent columns of the memory cell strings in the first array and two adjacent columns of the memory cell strings in the second array.

2. The apparatus of claim 1, wherein the multiple rows of memory cell strings in at least one of the arrays of the plurality of stacked memory arrays comprises four adjacent rows of memory cell strings.

3. The apparatus of claim 1, wherein the data plates comprise a first data plate and a second data plate, wherein multiple rows of memory cell strings of the first array are coupled to the first data plate, and wherein multiple rows of memory cell strings of the second array are coupled to the second data plate.

4. The apparatus of claim 3, further comprising:

a first data detector coupled to the first data plate, and a second data detector coupled to the second data plate.

5. The apparatus of claim 3, wherein each of the memory cell strings in the first array includes a plurality of select gates coupled between a memory cell region of the string and the first data plate.

6. The apparatus of claim 3, wherein each of the memory cell strings in the second array includes a plurality of select gates coupled between a memory cell region of the string and the second data plate.

7. The apparatus of claim 1, wherein the plurality of select gates includes a first select gate to select a respective row of blocks,

8. The apparatus of claim 7, wherein each of the blocks includes a memory cell string from the first array and a memory cell string from the second array.

9. The apparatus of claim 7, wherein the plurality of select gates includes a second select gate to select a respective column of blocks.

10. An apparatus, comprising:

a plurality of stacked memory arrays, including a first array of memory cell strings and a second array of memory cell strings stacked on top of the first array;

a data plate associated with multiple rows of memory cell strings of at least one of the plurality of stacked memory arrays; and

for each of the memory cell strings associated with the data plate, a plurality of select gates coupled between a memory cell region of the memory cell string and the data plate,

wherein the plurality of select gates includes a first select gate to select a respective row of blocks, and wherein a block in the respective row of blocks includes a memory cell string from the first array and a memory cell string from the second array.

11. The apparatus of claim 10, wherein the memory cell strings include NAND memory cell strings.

12. The apparatus of claim 10, wherein each of the memory cell strings includes a memory cell region, with a drain select gate disposed between the memory cell region and a data line to which the memory cell string is coupled.

13. The apparatus of claim 12, wherein the drain select gate comprises a plurality of hierarchical select gates coupled between the memory cell region of the memory cell string and the data line to which the memory cell string is coupled.

14. The apparatus of claim 10, wherein each of the memory cell strings includes a source select gate disposed between a memory cell region and a source to which the memory cell string is coupled.

15. The apparatus of claim 10, wherein the memory cell strings are vertically aligned with a vertical axis of the plurality of stacked memory arrays.

16. A method, comprising:

selecting a first memory cell string in a first array within a plurality of stacked arrays, wherein some memory cell strings of the first array are coupled between a first source and a shared data line;

detecting a first data state of a memory cell within the first memory cell string at a shared data detector;

selecting a second memory cell string in a second array within the plurality of stacked arrays; and

detecting a second data state of a memory cell within the second memory cell string at the shared data detector.

17. The method of claim 16, wherein detecting the first data state includes detecting the first data state through a first data line, and wherein detecting the second data state includes detecting the second data state through a second data line.

18. The method of claim 16, wherein detecting the first data state includes detecting the first data state through the shared data line.

19. The method of claim 16, wherein detecting the second data state includes detecting the second data state through the shared data line.

20. The method of claim 16, wherein memory strings of the second array are coupled between a second source and the shared data line, and substantially vertically aligned with memory strings of the first array.