SENSING MEMORY CELLS COUPLED TO DIFFERENT ACCESS LINES IN DIFFERENT BLOCKS OF MEMORY CELLS

• US 20150162090A1
• Filed: 12/11/2013
• Published: 06/11/2015
• Est. Priority Date: 12/11/2013
• Status: Active Grant

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: Sakui, Koji
• Granted Patent: US 9,070,470 B1
• Time in Patent Office: Days
• US Class Current: 1/1
• CPC Class Codes: G11C 16/0483 comprising cells having several storage transistors connected in series
• CPC Class Codes: G11C 16/10 Programming or data input circuits
• CPC Class Codes: G11C 16/14 Circuits for erasing electrically, e.g. erase voltage switching circuits
• CPC Class Codes: G11C 16/26 Sensing or reading circuits; Data output circuits
• CPC Class Codes: G11C 16/32 Timing circuits

Abstract

In an embodiment, a target memory cell in a first block of memory cells of a memory device and a target memory cell in a second block of memory cells of the memory device are sensed concurrently while a read voltage is applied to a selected access line coupled to the target memory cell in the first block of memory cells and while a read voltage is applied to another selected access line coupled to the target memory cell in the second block of memory cells.

Claims

1. A method of operating a memory device, comprising:

sensing a target memory cell in a first block of memory cells and a target memory cell in a second block of memory cells concurrently while applying a read voltage to a selected access line coupled to the target memory cell in the first block of memory cells and while applying a read voltage to another selected access line coupled to the target memory cell in the second block of memory cells;

wherein the target memory cell in the first block of memory cells and a memory cell in the second block of memory cells are each selectively coupled to a first data line; and

wherein the target memory cell in the second block of memory cells and a memory cell in the first block of memory cells are each selectively coupled to a second data line.

2. The method of claim 1, wherein sensing the target memory cell in the first block of memory cells and the target memory cell in the second block of memory cells concurrently comprises sensing the first data line selectively coupled to the target memory cell in the first block of memory cells and the second data line selectively coupled to the target memory cell in the second block of memory cells concurrently.

3. The method of claim 2, wherein the first data line is coupled to an activated select transistor coupled to a string of memory cells in the second block of memory cells, wherein the string of memory cells in the second block of memory cells comprises the memory cell in the second block of memory cells and wherein the memory cell in the second block of memory cells comprises an untargeted memory cell coupled to the selected access line coupled to the target memory cell in the second block of memory cells and a selector memory cell that isolates the untargeted memory cell from the first data line.

4. The method of claim 3, wherein the selector memory cell that isolates the untargeted memory cell from the first data line is coupled to a selector access line in the second block of memory cells that receives a voltage that is insufficient to activate the selector memory cell.

5. The method of claim 4, wherein the selector memory cell that isolates the untargeted memory cell from the first data line inhibits current from flowing through the untargeted memory cell to the first data line.

6. The method of claim 3, wherein the first data line is coupled to an activated select transistor coupled to a string of memory cells in the first block of memory cells, wherein the string of memory cells in the first block of memory cells comprises the target memory cell in the first block of memory cells and a selector memory cell that receives a voltage that activates the selector memory cell.

7. The method of claim 1, further comprising addressing the target memory cell in the first block of memory cells and the target memory cell in the second block of memory cells with a common page address.

8. A method of operating a memory device, comprising:

applying a first activation voltage to a first select line in a first block of memory cells that activates first and second select transistors in the first block of memory cells commonly coupled to the first select line, wherein the first select transistor is coupled to a first string of memory cells in the first block of memory cells and to a first data line and the second select transistor is coupled to a second string of memory cells in the first block of memory cells and to a second data line;

while applying the first activation voltage, applying a second activation voltage to a second select line in a second block of memory cells that activates third and fourth select transistors in the second block of memory cells commonly coupled to the second select line, wherein the third select transistor is coupled to a third string of memory cells in the second block of memory cells and to the first data line and the fourth select transistor is coupled to a fourth string of memory cells in the second block of memory cells and to the second data line;

coupling the first string of memory cells to the first data line while isolating the third string of memory cells from the first data line and while applying the first and second activation voltages; and

coupling the fourth string of memory cells to the second data line while isolating the second string of memory cells from the second data line, and while applying the first and second activation voltages;

wherein a selector memory cell in the third string of memory cells that is deactivated isolates the third string of memory cells from the first data line and a selector memory cell in the second string of memory cells that is deactivated isolates the second string of memory cells from the second data line.

9. The method of claim 8, wherein coupling the fourth string of memory cells to the second data line occurs while coupling the first string of memory cells to the first data line and while isolating the third string of memory cells from the first data line.

10. The method of claim 8, wherein the selector memory cell in the third string of memory cells and the selector memory cell in the second string of memory cells are not used to store user data or ECC.

11. The method of claim 8, further comprising:

applying a first read voltage to a selected access line commonly coupled to a target memory cell in the first string of memory cells and to an untargeted memory cell in the second string of memory cells while the first string is coupled to the first bit line; and

while applying the first read voltage, applying a second read voltage to another selected access line commonly coupled to an untargeted memory cell in the third string of memory cells and to a target memory cell in the fourth string of memory cells while the fourth string is coupled to the second bit line.

12. The method of claim 11, wherein target memory cell in the first string of memory cells and the target memory cell in the fourth string of memory cells are addressed by a common page address.

13. The method of claim 8, further comprising:

applying a first program voltage to a selected access line commonly coupled to a target memory cell in the first string of memory cells and to an untargeted memory cell in the second string of memory cells while the first string is coupled to the first data line; and

while applying the first program voltage, applying a second program voltage to another selected access line commonly coupled to an untargeted memory cell in the third string of memory cells and to a target memory cell in the fourth string of memory cells while the fourth string is coupled to the second data line.

14. The method of claim 13, wherein the selector memory cell in the second string of memory cells that is deactivated maintains a voltage on a channel of the untargeted memory cell in the second string of memory cells that inhibits the untargeted memory cell in the second string of memory cells from being programmed, and wherein the selector memory cell in the third string of memory cells that is deactivated maintains a voltage on a channel of the untargeted memory cell in the third string of memory cells that inhibits the untargeted memory cell in the third string of memory cells from being programmed.

15. The method of claim 8, further comprising, while applying the first and second activation voltages:

applying a first voltage to a first selector access line that is commonly coupled to a selector memory cell in the first string of memory cells and the selector memory cell in the second string of memory cells, wherein the first voltage activates the selector memory cell in the first string of memory cells and is insufficient to activate the selector memory cell in the second string of memory cells; and

applying a second voltage to a second selector access line that is commonly coupled to the selector memory cell in the third string of memory cells and a selector memory cell in the fourth string of memory cells wherein the second voltage activates the selector memory cell in the fourth string of memory cells and is insufficient to activate the selector memory cell in the third string of memory cells.

16. The method of claim 15, wherein the selector memory cell in the first string of memory cells and the selector memory cell in the second string of memory cells are respectively a first selector memory cell in the first string of memory cells and a first selector memory cell in the second string of memory cells, wherein the selector memory cell in the third string of memory cells and the selector memory cell in the fourth string of memory cells are respectively a first selector memory cell in the third string of memory cells and a first selector memory cell in the fourth string of memory cells, and further comprising, while applying the first and second activation voltages:

applying a third voltage to a third selector access line that is commonly coupled to a second selector memory cell in the first string of memory cells and a second selector memory cell in the second string of memory cells, wherein the third voltage activates the second selector memory cell in the first string of memory cells and the second selector memory cell in the second string of memory cells; and

applying a fourth voltage to a fourth selector access line that is commonly coupled to a second selector memory cell in the third string of memory cells and a second selector memory cell in the fourth string of memory cells wherein the fourth voltage activates the second selector memory cell in the third string of memory cells and the second selector memory cell in the fourth string of memory cells.

17. The method of claim 16, wherein the first selector memory cells in the first and fourth strings of memory cells are erased, wherein the first selector memory cells in the second and third strings of memory cells are programmed, wherein the second selector memory cells in the first and fourth strings are programmed, and the second selector memory cells in the second and third strings are erased.

18. A method of operating a memory device, comprising:

applying a first activation voltage to a first select line in a first block of memory cells that activates first and second select transistors in the first block of memory cells commonly coupled to the first select line, wherein the first select transistor is coupled to a first string of memory cells in the first block of memory cells and to a first data line and the second select transistor is coupled to a second string of memory cells in the first block of memory cells and to a second data line;

applying a first voltage to a first selector access line that is commonly coupled to a selector memory cell in the first string of memory cells and a selector memory cell in the second string of memory cells, wherein the first voltage activates the selector memory cell in the first string of memory cells and is insufficient to activate the selector memory cell in the second string of memory cells so that the selector memory cell in the second string of memory cells is deactivated and isolates the second string of memory cells from the second data line, wherein the first string of memory cells is coupled to the first data line through the activated selector memory cell in the first string of memory cells and the activated first select transistor;

applying a first read voltage to a selected access line in the first block of memory cells commonly coupled a target memory cell in the first string of memory cells and an untargeted memory cell in the second string of memory cells;

sensing the first data line while the first string of memory cells is coupled to the first data line, while the second string of memory cells is isolated from the second data line, and while applying the first read voltage;

applying a second activation voltage to a second select line in a second block of memory cells that activates third and fourth select transistors in the second block of memory cells commonly coupled to the second select line, wherein the third select transistor is coupled to a third string of memory cells in the second block of memory cells and to the first data line and the fourth select transistor is coupled to a fourth string of memory cells in the second block of memory cells and to the second data line;

applying a second voltage to a second selector access line that is commonly coupled to a selector memory cell in the third string of memory cells and a selector memory cell in the fourth string of memory cells, wherein the second voltage activates the selector memory cell in the fourth string of memory cells and is insufficient to activate the selector memory cell in the third string of memory cells so that the selector memory cell in the third string of memory cells is deactivated and isolates the third string of memory cells from the first data line, wherein the fourth string of memory cells is coupled to the second data line through the activated selector memory cell in the fourth string of memory cells and the activated fourth select transistor;

applying a second read voltage to a selected access line in the second block of memory cells commonly coupled a target memory cell in the fourth string of memory cells and an untargeted memory cell in the third string of memory cells; and

after sensing the first data line, sensing the second data line while the fourth string of memory cells is coupled to the second data line, while the third string of memory cells is isolated from the first data line, and while applying the second read voltage.

19. The method of claim 18, further comprising charging the first data line before sensing the first data line and leaving the second data line uncharged while sensing the first data line, and charging the second data line before sensing the second data line and leaving the first data line uncharged while sensing the second data line.

20. The method of claim 18, further comprising addressing the target memory cell in the first string of memory cells with a first page address and addressing the target memory cell in the fourth string of memory cells with a second page address different than the first page address.

21. A method of operating a memory device, comprising:

applying a first voltage to a first selector access line commonly coupled to a first selector memory cell in each of a first string, a second string, a third string, and a fourth string of series-coupled memory cells;

applying a second voltage to a second selector access line commonly coupled to a second selector memory cell in each of the first string, the second string, the third string, and the fourth string of series-coupled memory cells while applying the first voltage to the first selector access line;

applying a third voltage to a third selector access line commonly coupled to a third selector memory cell in each of the first string, the second string, the third string, and the fourth string of series-coupled memory cells while applying the first voltage to the first selector access line and the second voltage to the second selector access line; and

applying a fourth voltage to a fourth selector access line commonly coupled to a fourth selector memory cell in each of the first string, the second string, the third string, and the fourth string of series-coupled memory cells while applying the first voltage to the first selector access line, the second voltage to the second selector access line, and the third voltage to the third selector access line;

wherein the first voltage activates the first selector memory cell in each of the first string, the second string, the third string, and the fourth string of series-coupled memory cells;

wherein the second voltage activates the second selector memory cell in each of the first string and the third string of series-coupled memory cells and is insufficient to activate the second selector memory cell in each of the second string and the fourth string of series-coupled memory cells so that the second selector memory cell in each of the second string and the fourth string of series-coupled memory cells is deactivated;

wherein the third voltage activates the third selector memory cell in each of the first string, the second string, the third string, and the fourth string of series-coupled memory cells; and

wherein the fourth voltage activates the fourth selector memory cell in each of the first string and the second string of series-coupled memory cells and is insufficient to activate the fourth selector memory cell in each of the third string and the fourth string of series-coupled memory cells so that the fourth selector memory cell in each of the third string and the fourth string of series-coupled memory cells is deactivated.

22. The method of claim 21, wherein the first selector memory cell in each of the first string and the third string of series-coupled memory cells is programmed and the first selector memory cell in each of the second string and the fourth string of series-coupled memory cells is erased, wherein the second selector memory cell in each of the first string and the third string of series-coupled memory cells is erased and the second selector memory cell in each of the second string and the fourth string of series-coupled memory cells is programmed, wherein the third selector memory cell in each of the first string and the second string of series-coupled memory cells is programmed and the third selector memory cell in each of the third string and the fourth string of series-coupled memory cells is erased, and wherein the fourth selector memory cell in each of the first string and the second string of series-coupled memory cells is erased and the fourth selector memory cell in each of the third string and the fourth string of series-coupled memory cells is programmed.

23. The method of claim 21, further comprising activating a select transistor coupled between the first string of series-coupled memory cells and a first data line, a select transistor coupled between the second string of series-coupled memory cells and a second data line, a select transistor coupled between the third string of series-coupled memory cells and a third data line, and a select transistor coupled between the fourth string of series-coupled memory cells and a fourth data line while applying the first, second, third, and fourth voltages.

24. The method of claim 23, wherein the activated first selector memory cell, the activated second selector memory cell, the activated third selector memory cell, and the activated fourth selector memory cell in the first string of series-coupled memory cells couple the first string of series-coupled memory cells to the first data line through the activated first select transistor, wherein the second selector memory cell in the second string of series-coupled memory cells that is deactivated isolates the second string of series-coupled memory cells from the second data line, wherein the fourth selector memory cell in the third string of series-coupled memory cells that is deactivated isolates the third string of series-coupled memory cells from the third data line, and wherein the fourth selector memory cell in the fourth string of series-coupled memory cells that is deactivated isolates the fourth string of series-coupled memory cells from the fourth data line.

25. The method of claim 24, further comprising sensing the first data line while the first string of series-coupled memory cells is coupled to the first data line, while applying the first, second, third, and fourth voltages, and while a read voltage is applied to an access line that is commonly coupled to a fifth memory cell in each of the first string, the second string, the third string, and the fourth string of series-coupled memory cells.

26. A memory device, comprising:

first and second blocks of memory cells; and

a controller;

wherein the controller is configured to cause the memory device to sense a target memory cell in the first block of memory cells and a target memory cell in the second block of memory cells concurrently while a read voltage is being applied to a selected access line coupled to the target memory cell in the first block of memory cells and while a read voltage is being applied to another selected access line coupled to the target memory cell in the second block of memory cells;

wherein the target memory cell in the first block of memory cells and a memory cell in the second block of memory cells are each selectively coupled to a first data line; and

wherein the target memory cell in the second block of memory cells and a memory cell in the first block of memory cells are each selectively coupled to a second data line.

27. The memory device of claim 26, wherein the target memory cell in the first block of memory cells is in a first string of series-coupled memory cells in the first block of memory cells, wherein the first string of series-coupled memory cells in the first block of memory cells is coupled to a first select transistor coupled to the first data line, wherein the first data line is coupled to a second select transistor coupled to a first string of series-coupled memory cells in the second block of memory cells, wherein the first string of series-coupled memory cells in the second block of memory cells comprises a memory cell coupled to the access line coupled to the target memory cell in the second block of memory cells and a first selector memory cell, wherein the first selector memory cell is programmed to remain deactivated and thereby isolate the first string of series-coupled memory cells in the second block of memory cells from the first data line when the first and second select transistors are activated and when the target memory cell in the first block of memory cells is being sensed by sensing the first data line.

28. The memory device of claim 27, wherein the target memory cell in the second block of memory cells is in a second string of series-coupled memory cells in the second block of memory cells, wherein the second string of series-coupled memory cells in the second block of memory cells is coupled to a third select transistor coupled to the second data line, wherein the second data line is coupled to a fourth select transistor coupled to a second string of series-coupled memory cells in the first block of memory cells, wherein the second string of series-coupled memory cells in the first block of memory cells comprises a memory cell coupled to the access line coupled to the target memory cell in the first block of memory cells and a second selector memory cell, wherein the second selector memory cell is programmed to remain deactivated and thereby isolate the second string of series-coupled memory cells in the first block of memory cells from the second data line when the first, second, third, and fourth select transistors are activated and when the target memory cell in the second block of memory cells is being sensed by sensing the second data line.

29. The memory device of claim 28, wherein the first string of series-coupled memory cells in the first block of memory cells comprises a third selector memory cell that is coupled to a first selector access line that is coupled to the second selector memory cell in the second string of series-coupled memory cells in the first block of memory cells, wherein the third selector memory cell is erased, and wherein the controller is configured to cause the memory device to apply a voltage to the first selector access line, while the first and second read voltages are being applied, that activates the third selector memory cell and that is insufficient to activate the second selector memory cell.

30. The memory device of claim 29, wherein the first string of series-coupled memory cells in the first block of memory cells comprises a fourth selector memory cell and the second string of series-coupled memory cells in the first block of memory cells comprises a fifth selector memory cell, wherein the fourth and fifth selector memory cells are coupled to a second selector access line, wherein the fourth selector memory cell is programmed and the fifth selector memory cell is erased, and wherein the controller is configured to cause the memory device to apply a voltage, while the first and second read voltages are being applied, to the second selector access line that activates the fourth and fifth selector memory cells.

31. The memory device of claim 30, wherein the second string of series-coupled memory cells in the second block of memory cells comprises a sixth selector memory cell that is coupled to a third selector access line that is coupled to the first selector memory cell in the first string of series-coupled memory cells in the second block of memory cells, wherein the sixth selector memory cell is erased, and wherein controller is configured to cause the memory device to apply a voltage to the third selector access line, while the first and second read voltages are being applied, that activates the sixth selector memory cell and that is insufficient to activate the first selector memory cell.

32. The memory device of claim 31, wherein the second string of series-coupled memory cells in the second block of memory cells comprises a seventh selector memory cell and the first string of series-coupled memory cells in the second block of memory cells comprises a eighth selector memory cell, wherein the seventh and eighth selector memory cells are coupled to a fourth selector access line, wherein the seventh selector memory cell is programmed and the eighth selector memory cell is erased, and wherein the controller is configured to cause the memory device to apply a voltage, while the first and second read voltages are being applied, to the fourth selector access line that activates the seventh and eighth selector memory cells.

33. A memory device, comprising:

first and second blocks of memory cells; and

a controller;

wherein the controller is configured to cause the memory device to apply a first activation voltage to a first select line in the first block of memory cells that activates first and second select transistors in the first block of memory cells commonly coupled to the first select line, wherein the first select transistor is coupled to a first string of memory cells in the first block of memory cells and to a first data line and the second select transistor is coupled to a second string of memory cells in the first block of memory cells and to a second data line;

wherein the controller is configured to cause the memory device to apply a second activation voltage, while the first activation voltage is applied, to a second select line in the second block of memory cells that activates third and fourth select transistors in the second block of memory cells commonly coupled to the second select line, wherein the third select transistor is coupled to a third string of memory cells in the second block of memory cells and to the first data line and the fourth select transistor is coupled to a fourth string of memory cells in the second block of memory cells and to the second data line;

wherein the controller is configured to cause the memory device to couple the first string of memory cells to the first data line while the third string of memory cells is isolated from the first data line and while the first and second activation voltages are applied;

wherein the controller is configured to cause the memory device to couple the fourth string of memory cells to the second data line while the second string of memory cells is isolated from the second data line, while the first and second activation voltages are being applied, while the first string of memory cells is coupled to the first data line, and while the third string of memory cells is isolated from the first data line;

wherein a selector memory cell in the third string of memory cells that is deactivated isolates the third string of memory cells from the first data line and a selector memory cell in the second string of memory cells that is deactivated isolates the second string of memory cells from the second data line.

34. The memory device of claim 33,

wherein the controller is configured to cause the memory device to apply a first read voltage to a selected access line commonly coupled to a target memory cell in the first string of memory cells and to an untargeted memory cell in the second string of memory cells while the first string is coupled to the first data line;

and

wherein the controller is configured to cause the memory device to apply, while the first read voltage is applied, a second read voltage to another selected access line commonly coupled to an untargeted memory cell in the third string of memory cells and to a target memory cell in the fourth string of memory cells while the fourth string is coupled to the second data line.

35. The memory device of claim 33,

wherein the controller is configured to cause the memory device to apply a first program voltage to a selected access line commonly coupled to a target memory cell in the first string of memory cells and to an untargeted memory cell in the second string of memory cells while the first string is coupled to the first data line;

and

wherein the controller is configured to cause the memory device to apply, while the first program voltage is applied, a second program voltage to another selected access line commonly coupled to an untargeted memory cell in the third string of memory cells and to a target memory cell in the fourth string of memory cells while the fourth string is coupled to the second data line.

36. The memory device of claim 33,

wherein while the first and second activation voltages are applied, the controller is further configured to cause the memory device to apply a voltage to a first selector access line that is commonly coupled to a selector memory cell in the first string of memory cells and the selector memory cell in the second string of memory cells, wherein the voltage applied to the first selector access line activates the selector memory cell in the first string of memory cells and is insufficient to activate the selector memory cell in the second string of memory cells;

and

wherein while the first and second activation voltages are applied, the controller is further configured to cause the memory device to apply a voltage to a second selector access line that is commonly coupled to the selector memory cell in the third string of memory cells and a selector memory cell in the fourth string of memory cells wherein the voltage applied to the second selector access line activates the selector memory cell in the fourth string of memory cells and is insufficient to activate the selector memory cell in the third string of memory cells.

37. The memory device of claim 36, wherein the selector memory cell in the first string of memory cells is erased, wherein the selector memory cell in the second string of memory cells is programmed, wherein the selector memory cell in the fourth string of memory cells is erased, and wherein the selector memory cell in the third string of memory cells is programmed.

38. A memory device, comprising:

first and second data lines;

a first memory block comprising a first string of series-coupled memory cells coupled to a first select transistor coupled to the first data line and a second string of series-coupled memory cells coupled to a second select transistor coupled to the second data line;

a second memory block comprising a third string of series-coupled memory cells coupled to a third select transistor coupled to the first data line and a fourth string of series-coupled memory cells coupled to a fourth select transistor coupled to the second data line;

a first selector access line in the first memory block commonly coupled to a first selector memory cell in the first string of series-coupled memory cells and a first selector memory cell in the second string of series-coupled memory cells; and

a second selector access line in the second memory block commonly coupled to a first selector memory cell in the third string of series-coupled memory cells and a first selector memory cell in the fourth string of series-coupled memory cells;

wherein the first selector access line is configured to receive a voltage that activates the first selector memory cell in the first string of series-coupled memory cells and that is insufficient to activate the first selector memory cell in the second string of series-coupled memory cells so that the first selector memory cell in the second string of series-coupled memory cells isolates the second string of series-coupled memory cells from the second data line while the first, second, third and fourth select transistors are activated and while the first string of series-coupled memory cells is coupled to the first data line; and

wherein the second selector access line is configured to receive a voltage that activates the first selector memory cell in the fourth string of series-coupled memory cells and that is insufficient to activate the first selector memory cell in the third string of series-coupled memory cells so that the first selector memory cell in the third string of series-coupled memory cells isolates the third string of series-coupled memory cells from the first data line while the first, second, third and fourth select transistors are activated and while the first string of series-coupled memory cells is coupled to the first data line and the fourth string of series-coupled memory cells is coupled to the second data line.

39. The memory device of claim 38, wherein the first selector cells in the first, second, third, and fourth strings of series-coupled memory cells are not used to store user data or ECC.

40. The memory device of claim 38, further comprising:

an access line in the first memory block, configured to receive a first read voltage, commonly coupled to another memory cell in the first string of series-coupled memory cells and another selector memory cell in the second string of series-coupled memory cells; and

an access line in the second memory block, configured to receive a second read voltage, commonly coupled to another memory cell in the third string of series-coupled memory cells and another memory cell in the fourth string of series-coupled memory cells;

wherein the first and second data lines are configured to be sensed concurrently, while the first string of series-coupled memory cells is coupled to the first data line and the fourth string of series-coupled memory cells is coupled to the second data line, while the first selector memory cell in the second string of series-coupled memory cells isolates the second string of series-coupled memory cells from the second data line, and while the first selector memory cell in the third string of series-coupled memory cells isolates the third string of series-coupled memory cells from the first data line.

41. The memory device of claim 38, further comprising:

an access line in the first memory block, configured to receive a first program voltage, commonly coupled to an other memory cell in the first string of series-coupled memory cells and an other memory cell in the second string of series-coupled memory cells; and

an access line in the second memory block, configured to receive a second program voltage, commonly coupled to an other memory cell in the third string of series-coupled memory cells and an other memory cell in the fourth string of series-coupled memory cells;

wherein the first selector memory cell in the second string of series-coupled memory cells that isolates the second string of series-coupled memory cells from the second data line is configured to maintain a voltage on a channel of the other memory cell in the second string of series-coupled memory cells that inhibits the other memory cell in the second string of series-coupled memory cells from being programmed, and wherein the first selector memory cell in the third string of series-coupled memory cells that isolates the third string of series-coupled memory cells from the first data line maintains a voltage on a channel of the other memory cell in the third string of series-coupled memory cells that inhibits the other memory cell in the third string of series-coupled memory cells from being programmed.

42. The memory device of claim 38, further comprising:

a third selector access line in the first memory block commonly coupled to a second selector memory cell in the first string of series-coupled memory cells and a second selector memory cell in the second string of series-coupled memory cells; and

a fourth selector access line in the second memory block commonly coupled to a second selector memory cell in the third string of series-coupled memory cells and a second selector memory cell in the fourth string of series-coupled memory cells;

wherein the third selector access line is configured to receive a voltage that activates the second selector memory cell in the first string of series-coupled memory cells and the second selector memory cell in the second string of series-coupled memory cells; and

wherein the fourth selector access line is configured to receive a voltage that activates the second selector memory cell in the third string of series-coupled memory cells and the second selector memory cell in the fourth string of series-coupled memory cells.

43. An apparatus, comprising:

a block of memory cells comprising a plurality of strings of series-coupled memory cells, wherein each of the strings of series-coupled memory cells comprises a set of dummy memory cells responsive to a set of control signals and a set of data memory cells;

wherein, in response to the set of control signals having a first set of voltages, reading of data memory cells is enabled for only a first portion of the plurality of strings of series-coupled memory cells;

wherein, in response to the set of control signals having a second set of voltages, reading of data memory cells is enabled for only a second portion of the plurality of strings of series-coupled memory cells; and

wherein, in response to the set of control signals having a third set of voltages, reading of data memory cells is enabled for the first portion and the second portion of the plurality of strings of series-coupled memory cells.

44. The apparatus of claim 43, further comprising:

wherein, in response to the set of control signals having a fourth set of voltages, reading of data memory cells is enabled for only a third portion of the plurality of strings of series-coupled memory cells; and

wherein, in response to the set of control signals having the third set of voltages, reading of data memory cells is enabled for the first portion, the second portion and the third portion of the plurality of strings of series-coupled memory cells.

45. The apparatus of claim 43, further comprising:

wherein the first portion of the plurality of strings of series-coupled memory cells are contained within a first contiguous set of strings of series-coupled memory cells of the plurality of strings of series-coupled memory cells; and

wherein the second portion of the plurality of strings of series-coupled memory cells are contained within a second contiguous set of strings of series-coupled memory cells of the plurality of strings of series-coupled memory cells.

46. The apparatus of claim 45, wherein the first portion of the plurality of strings of series-coupled memory cells comprises every other string of series-coupled memory cells contained within the first contiguous set of strings of series-coupled memory cells, and wherein the second portion of the plurality of strings of series-coupled memory cells comprises every other string of series-coupled memory cells contained within the second contiguous set of strings of series-coupled memory cells.

47. The apparatus of claim 43, wherein a string of series-coupled memory cells of the first portion of the plurality of strings of series-coupled memory cells is interposed between strings of series-coupled memory cells of the second portion of the plurality of strings of series-coupled memory cells.