SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME

• US 20150162342A1
• Filed: 05/20/2014
• Published: 06/11/2015
• Est. Priority Date: 12/09/2013
• Status: Active Grant

• Current Assignee: SK Hynix Inc.
• Original Assignee: SK Hynix Inc.
• Inventors: LEE, Ki Hong, PYI, Seung Ho, LEE, Seung Jun
• Granted Patent: US 10,283,518 B2
• Time in Patent Office: Days
• US Class Current: 1/1
• CPC Class Codes: H01L 29/66666 Vertical transistors H01L29/66712, H01L29/66742 take precedence
• CPC Class Codes: H01L 29/66833 with a charge trapping gate insulator, e.g. MNOS transistors
• CPC Class Codes: H01L 29/7926 Vertical transistors, i.e. transistors having source and drain not in the same horizontal plane
• CPC Class Codes: H10B 43/27 the channels comprising vertical portions, e.g. U-shaped channels
• CPC Class Codes: H10B 43/40 characterised by the peripheral circuit region

Abstract

A semiconductor device includes a first stacked structure having first conductive layers and first insulating layers formed alternately with each other, first semiconductor patterns passing through the first stacked structure, a coupling pattern coupled to the first semiconductor patterns, and a slit passing through the first stacked structure and the coupling pattern.

Claims

1. A semiconductor device, comprising:

a first stacked structure including first conductive layers and first insulating layers formed alternately with each other;

first semiconductor patterns passing through the first stacked structure;

a coupling pattern coupled to the first semiconductor patterns; and

a slit passing through the first stacked structure and the coupling pattern.

2. The semiconductor device of claim 1, wherein the coupling pattern comprises:

a horizontal portion coupled to lower portions of the first semiconductor patterns; and

vertical portions protruding from the horizontal portion and surrounding sidewalls of the first semiconductor patterns.

3. The semiconductor device of claim 2, wherein each of the vertical portions surrounds each of the first semiconductor patterns at a uniform height.

4. The semiconductor device of claim 2, wherein each of the vertical portions surrounds each of the first semiconductor patterns at a non-uniform height.

5. The semiconductor device of claim 2, further comprising multilayer dielectric layers surrounding the sidewalls of the first semiconductor patterns and having substantially the same thickness as the vertical portions.

6. The semiconductor device of claim 1, wherein the coupling pattern has is substantially conductive.

7. The semiconductor device of claim 1, further comprising a protective layer contacting a top surface of the coupling pattern and including a different material from the coupling pattern.

8. The semiconductor device of claim 1, further comprising multilayer dielectric layers surrounding sidewalls of the first semiconductor patterns.

9. The semiconductor device of claim 8, wherein a thickness of the coupling pattern is less than twice the thickness of the multilayer dielectric layer.

10. The semiconductor device of claim 8, wherein each of the multilayer dielectric layers includes a tunnel insulating layer, a data storage layer and a charge blocking layer.

11. The semiconductor device of claim 10, wherein a thickness of the coupling pattern is more than twice as much as a sum of thicknesses of the charge blocking layer and the data storage layer and less than twice as much as a sum of thicknesses of the charge blocking layer, the data storage layer and the tunnel insulating layer.

12. The semiconductor device of claim 10, wherein a thickness of the coupling pattern is more than twice as much as a thickness of the charge blocking layer and less than twice as much as a sum of thicknesses of the charge blocking layer and the data storage layer.

13. The semiconductor device of claim 10, wherein top surfaces of the tunnel insulating layer, the data storage layer and the charge blocking layer have different heights, and

wherein each of the first semiconductor patterns includes:

an insulating layer passing through the first stacked structure;

a semiconductor plug formed on the insulating layer; and

a semiconductor layer surrounding a sidewall of the insulating layer and passing through the semiconductor plug.

14. The semiconductor device of claim 1, further comprising a peripheral circuit located under the first stacked structure.

15. The semiconductor device of claim 1, further comprising:

a second stacked structure located under the first stacked structure and including second conductive layers and second insulating layers formed alternately with each other; and

second semiconductor patterns passing through the second stacked structure and coupled to the first semiconductor patterns through the coupling pattern.

16. The semiconductor device of claim 15, wherein the first semiconductor patterns, the coupling pattern and the second semiconductor patterns are channel layers.

17. The semiconductor device of claim 15, further comprising:

a third semiconductor pattern coupling at least two of the second semiconductor patterns; and

a third conductive layer surrounding the third semiconductor pattern.

18. The semiconductor device of claim 15, wherein each of the second semiconductor patterns includes a groove formed in a top surface thereof, and

wherein the groove is filled with the coupling pattern.

19. The semiconductor device of claim 1, wherein the coupling pattern is a first source layer.

20. The semiconductor device of claim 19, further comprising:

a third insulating layer surrounding the coupling pattern; and

a substrate located under the third insulating layer and contacting a bottom surface of the coupling pattern.

21. The semiconductor device of claim 20, wherein the substrate includes a groove formed in a top surface thereof, and

wherein the groove is filled with the coupling pattern.

22. The semiconductor device of claim 19, further comprising:

a second source layer surrounding the first source layer and including polysilicon;

a third insulating layer located under the second source layer; and

a substrate located under the third insulating layer.

23. The semiconductor device of claim 22, further comprising a third source layer interposed between the second source layer and the third insulating layer, and including a metal layer.

24. The semiconductor device of claim 23, further comprising a fourth source layer interposed between the third source layer and the third insulating layer, and including polysilicon.

25. The semiconductor device of claim 19, further comprising:

a peripheral circuit located under the first stacked structure;

a first contact plug coupling the peripheral circuit and the first semiconductor patterns to each other; and

a second contact plug coupling the peripheral circuit and the first source layer to each other.

26. A semiconductor device, comprising:

a first stacked structure including first gate electrodes and first insulating layers formed alternately with each other;

a second stacked structure located under the first stacked structure, and including second gate electrodes and second insulating layers formed alternately with each other;

first channel layers passing through the first stacked structure;

second channel layers passing through the second stacked structure;

a coupling pattern including a horizontal portion coupled to lower portions of the first channel layers and upper portions of the second channel layers and vertical portions protruding from the horizontal portion and surrounding sidewalls of the first channel layers; and

a slit passing through the first stacked structure, the second stacked structure and the horizontal portion of the coupling pattern.

27. The semiconductor device of claim 26, further comprising a tunnel insulating layer, a data storage layer and a charge blocking layer surrounding each of the second channel layers, wherein heights of top surfaces of the tunnel insulating layer, the data storage layer and the charge blocking layer are different,

wherein each of the second channel layers includes:

an Insulating layer passing through the second stacked structure;

a semiconductor plug formed on the insulating layer; and

a semiconductor layer surrounding a sidewall of the insulating layer and passing through the semiconductor plug.

28. A method of manufacturing a semiconductor device, the method comprising:

forming a sacrificial pattern;

forming a first stacked structure over the sacrificial pattern, wherein the first stacked structure includes first material layers and second material layers formed alternately with each other;

forming first openings passing through the first stacked structure;

removing the sacrificial pattern through the first openings to form a second opening;

forming a multilayer dielectric layer in the first and second openings to fill the second opening; and

forming first semiconductor patterns in the first openings.

29. The method of claim 28, further comprising:

forming a slit passing through the first stacked structure and the second opening;

removing a portion of the multilayer dielectric layer exposed through the slit to form a third opening; and

forming a coupling pattern in the third opening.

30. The method of claim 29, wherein the removing of the portion of the multilayer dielectric layer comprises completely removing the multilayer dielectric layer formed in the second opening, and partially removing the multilayer dielectric layer formed in the first openings.

31. The method of claim 28, wherein the forming of the multilayer dielectric layer comprises:

forming a charge blocking layer in the first and second openings;

forming a data storage layer in the first and second openings, in which the charge blocking layer is formed; and

forming a tunnel insulating layer in the first and second openings, in which the data storage layer is formed, in order to completely fill the second opening.

32. The method of claim 28, wherein the forming of the multilayer dielectric layer comprises:

forming a charge blocking layer in the first and second openings;

forming a data storage layer in the first and second openings, in which the charge blocking layer is formed, in order to completely fill the second opening; and

forming a tunnel insulating layer in the first openings, in which the data storage layer is formed.

33. The method of claim 29, wherein the coupling pattern includes a horizontal portion coupled to lower portions of the first semiconductor patterns and vertical portions protruding from the horizontal portion and surrounding sidewalls of the first semiconductor patterns.

34. The method of claim 29, further comprising:

forming a second stacked structure including third material layers and fourth material layers formed alternately with each other, before the forming of the sacrificial pattern; and

forming second semiconductor patterns passing through the second stacked structure.

35. The method of claim 34, wherein the forming of the coupling pattern comprises:

growing a polysilicon layer from the first semiconductor pattern or the second semiconductor pattern; and

siliciding the polysilicon layer.