SEMICONDUCTOR STRUCTURE AND METHOD FOR MANUFACTURING THE SAME

• US 20150162415A1
• Filed: 11/23/2011
• Published: 06/11/2015
• Est. Priority Date: 11/23/2011
• Status: Active Grant

• Current Assignee: Institute of Microelectronics Chinese Academy of Sciences (Chinese Academy of Sciences)
• Original Assignee: Institute of Microelectronics Chinese Academy of Sciences (Chinese Academy of Sciences)
• Inventors: Yin, Haizhou, Xu, Jing, Liu, Yunfei
• Granted Patent: US 9,209,269 B2
• Time in Patent Office: Days
• US Class Current: 1/1
• CPC Class Codes: H01L 21/28518 the conductive layers comprising silicides H01L21/28537 takes precedence
• CPC Class Codes: H01L 21/324 Thermal treatment for modifying the properties of semiconductor bodies, e.g. annealing, sintering H01L21/20 - H01L21/288 and H01L21/302 - H01L21/322 take precedence
• CPC Class Codes: H01L 29/458 for thin film silicon, e.g. source or drain electrode
• CPC Class Codes: H01L 29/665 using self aligned silicidation, i.e. salicide formation of conductive layers comprising silicides H01L21/28518
• CPC Class Codes: H01L 29/66772 Monocristalline silicon transistors on insulating substrates, e.g. quartz substrates H01L29/66666 takes precedence; thin film FinFETs H01L29/66795
• CPC Class Codes: H01L 29/78603 characterised by the insulating substrate or support H01L29/78657 takes precedence
• CPC Class Codes: H01L 29/78618 characterised by the drain or the source properties, e.g. the doping structure, the composition, the sectional shape or the contact structure silicide contacts, electrodes in general H01L29/458

Abstract

A method for manufacturing a semiconductor structure comprises following steps: providing an SOI substrate, forming a gate stack on the SOI substrate, forming sidewall spacers on sidewalls of the gate stack, and forming source/drain regions on each side of the gate stack; depositing a first metal layer on surfaces of an entire semiconductor structure, and then removing the first metal layer; forming an amorphous semiconductor layer on surfaces of the source/drain regions; depositing a second metal layer on surfaces of the entire semiconductor structure, and then removing the second metal layer; and annealing the semiconductor structure. Accordingly, the present invention further provides a semiconductor structure. The present invention is capable of effectively reducing contact resistance at source/drain regions.

Claims

1. A method of manufacturing a semiconductor structure, comprising:

a) providing an SOI substrate, forming a gate stack on the SOI substrate, forming sidewall spacers (240) on sidewalls of the gate stack, and forming source/drain regions (131) on each side of the gate stack;

b) depositing a first metal layer (300) on surfaces of the entire semiconductor structure, and then removing the first metal layer (300);

c) forming an amorphous semiconductor layer (400) on surfaces of the source/drain regions (131);

d) depositing a second metal layer (500) on surfaces of an entire semiconductor structure, and then removing the second metal layer (500); and

e) annealing the semiconductor structure.

2. The manufacturing method of claim 1, wherein steps c) and d) are implemented at least twice after implementation of the step b).

3. The manufacturing method of claim 1, wherein the semiconductor structure is annealed immediately after the first metal layer (300) or the second metal layer (500) is removed.

4. The manufacturing method of claim 1, wherein

the material of the first metal layer (300) and/or the second metal layers (500) comprises Ni or NiPt.

5. The manufacturing method of claim 3, wherein

after the semiconductor is annealed, a first contact layer (310) is formed on surfaces of the source/drain regions (131) and/or second contact layers (410) are formed on the upper surface of each amorphous semiconductor layers (400);

wherein, the first contact layer (310) and/or the second contact layers (410) have a thickness of 2 nm.

6. The manufacturing method of claim 5, wherein

the first contact layer (310) and/or the second contact layers (410) comprise(s) NiSi or Ni(Pt)Si_2-y.

7. The manufacturing method of claim 1, wherein the step for forming the amorphous semiconductor layer (400) on surfaces of the source/drain regions (131) comprises:

depositing an amorphous semiconductor (250) to cover the semiconductor structure;

doping the amorphous semiconductor (250), wherein the type of dopants is the same as the type of a semiconductor device intended to manufacture;

removing a part of the amorphous semiconductor (250), and keeping the amorphous semiconductor layer (400) on surfaces of the source/drain regions (131).

8. The method of claim 7, wherein the amorphous semiconductor layers (400) are amorphous Si layers.

9. The method of claim 7, wherein the amorphous semiconductor layers (400) have a thickness between 3 nm to 5 nm.

10. A semiconductor structure comprising:

an SOI substrate;

a gate stack located on the SOI substrate;

sidewall spacers (240) located on sidewalls of the gate stack;

source/drain regions (131) located on each side of the gate stack, wherein;

a first contact layer (310) is arranged on surfaces of the source/drain regions (131); and

one or more layer(s) of amorphous semiconductor layers (400) are arranged on the source/drain regions (131), and second contact layers (410) are arranged on the surface of each amorphous semiconductor layer (400).

11. The semiconductor structure of claim 10, wherein

the first contact layer (310) and/or the second contact layers (410) have a thickness of 2 nm.

12. The semiconductor structure of claim 10, wherein

the first contact layer (310) and/or the second contact layers (410) comprise(s) NiSi or Ni(Pt)Si_2-y.

13. The semiconductor structure of claim 10, wherein the amorphous semiconductor layers (400) are amorphous Si layers.

14. The semiconductor structure of claim 13, wherein the amorphous semiconductor layers (400) have a thickness in the range of 3 nm to 5 nm.