FINFET WITH ISOLATION

• US 20150162436A1
• Filed: 12/11/2013
• Published: 06/11/2015
• Est. Priority Date: 12/11/2013
• Status: Active Grant

• Current Assignee: Alsephina Innovations Inc. (Quarterhill Inc. (f/k/a Wi-LAN Inc.))
• Original Assignee: Globalfoundries Singapore Pte Limited (GlobalFoundries, Inc.)
• Inventors: TOH, Eng Huat, TAN, Shyue Seng, QUEK, Elgin Kiok Boone
• Granted Patent: US 9,620,642 B2
• Time in Patent Office: Days
• US Class Current: 1/1
• CPC Class Codes: H01L 21/76205 in a region being recessed from the surface, e.g. in a recess, groove, tub or trench region
• CPC Class Codes: H01L 2221/1047 the air gaps being formed by pores in the dielectric
• CPC Class Codes: H01L 29/66545 using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate
• CPC Class Codes: H01L 29/66795 with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/785 having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/7851 with the body tied to the substrate

Abstract

Devices and methods for forming a device are presented. The method includes providing a substrate prepared with a device region. A fin is formed in the device region. The fin includes top and bottom portions. An isolation layer is formed on the substrate. The isolation layer has a top isolation surface disposed below a top fin surface, leaving an upper fin portion exposed. At least one isolation buffer is formed in the bottom fin portion, leaving the top fin portion crystalline, the top fin portion serves as a body of a fin type transistor. Source/drain (S/D) regions are formed in the top portions of the fin and a gate wrapping around the fin is provided.

Claims

1. A method for forming a device comprising:

providing a substrate prepared with a device region;

forming a fin in the device region, the fin includes top and bottom portions;

forming an isolation layer on the substrate, wherein the isolation layer has a top isolation surface disposed below a top fin surface, leaving an upper fin portion exposed;

forming at least one isolation buffer in the bottom fin portion, leaving the top fin portion crystalline, the top fin portion serves as a body of a fin type transistor;

forming source/drain (S/D) regions in the top portions of the fin; and

forming a gate wrapping around the fin.

2. The method of claim 1 wherein the isolation layer comprises an initial thickness T₁ and forming the fin comprises:

providing a patterned hard mask having a shape correspond to the fin; and

removing portions of the substrate unprotected by the hard mask to form the fin.

3. The method of claim 2 comprising:

forming a dummy gate over the substrate; and

forming protective liners after forming the dummy gate.

4. The method of claim 3 wherein the dummy gate is formed by:

providing a dummy gate layer over the substrate;

providing a patterned gate hard mask having a shape corresponding to the dummy gate; and

removing portions of the dummy gate layer unprotected by the gate hard mask to form the dummy gate.

5. The method of claim 4 wherein the at least one isolation buffer comprises first and second isolation buffers under the S/D regions.

6. The method of claim 5 wherein the protective liners are formed on sidewalls of the dummy gate and the first and second isolation buffers are formed by:

recessing the isolation layer below the protective liners to reduce the thickness of the isolation layer from T₁ to T₂;

doping exposed portions of the fin in between the protective liner and top surface of the recessed isolation layer; and

performing an oxidation process to the exposed doped fin portions to form first and second oxide isolation buffers.

7. The method of claim 6 wherein dummy gate protects the bottom fin portion from being oxidized.

8. The method of claim 7 comprising:

performing an etch to remove the first and second oxide isolation buffers to form the first and second isolation buffers below the S/D regions, wherein the isolation buffers are voids.

9. The method of claim 7 comprising:

removing the protective liners after forming the isolation buffers;

forming sidewall spacers on exposed sidewalls of the dummy gate; and

forming raised S/D regions on the S/D regions.

10. The method of claim 9 comprising:

forming an interlevel dielectric (ILD) layer on the substrate covering the fin, dummy gate and isolation layer;

performing a planarization process to form a top ILD surface which is about co-planar with top surface of the dummy gate; and

removing the dummy gate after the planarization process.

11. The method of claim 4 wherein the at least one isolation buffer is disposed under a channel region below the gate.

12. The method of claim 11 comprising:

forming sidewall spacers on sidewalls of the dummy gate prior to forming the S/D regions; and

forming raised S/D regions on the S/D regions.

13. The method of claim 12 comprising:

forming an interlevel dielectric (ILD) layer on the substrate covering the fin, dummy gate and isolation layer;

performing a planarization process to form a top ILD surface which is about co-planar with top surface of the dummy gate; and

removing the dummy gate after the planarization process to form a gate trench and exposes the sidewall spacers.

14. The method of claim 13 wherein the protective liners are formed in the gate trench over the exposed sidewall spacers and the isolation buffer under the channel region is formed by:

recessing the isolation layer below the protective liners to reduce the thickness of the isolation layer from T₁ to T₂;

doping exposed portion of the fin in between the protective liner and top surface of the recessed isolation layer; and

performing an oxidation process to the exposed doped fin portions to form an oxide isolation buffer.

15. The method of claim 14 comprising:

performing an etch to remove the oxide isolation buffer to form the isolation buffer below the channel region, wherein the isolation buffer is a void.

16. A device comprising:

a substrate prepared with a device region;

a fin in the device region, the fin includes top and bottom portions;

an isolation layer on the substrate, wherein the isolation layer has a top isolation surface disposed below a top fin surface, leaving an upper fin portion exposed;

at least one isolation buffer in the bottom fin portion, leaving the top fin portion crystalline, the top fin portion serves as a body of a fin type transistor;

source/drain (S/D) regions disposed in the top portions of the fin; and

a gate wrapping around the fin.

17. The device of claim 16 wherein the at least one isolation buffer comprises first and second isolation buffers disposed below the S/D regions.

18. The device of claim 16 wherein the at least one isolation buffer is disposed below a channel region under the gate.

19. The device of claim 16 wherein the at least one isolation buffer comprises oxide isolation buffer or void.

20. The device of claim 16 wherein the gate comprises top and side regions, wherein the top gate region is disposed over the fin and the side gate region extends from top surface of the fin to the top isolation surface, wherein bottom of the side gate region extends below bottom of the S/D regions.