INTEGRATED CIRCUIT DEVICE WITH POWER GATING SWITCH IN BACK END OF LINE

• US 20150162448A1
• Filed: 12/09/2014
• Published: 06/11/2015
• Est. Priority Date: 12/10/2013
• Status: Abandoned Application

• Current Assignee: IMEC International
• Original Assignee: IMEC International
• Inventors: Raghavan, Praveen, Genoe, Jan, Steudel, Soeren
• Application Number:
  US14/565,159
• Publication Number:
  US 20150162448A1
• Time in Patent Office: Days
• US Class Current: 1/1
• CPC Class Codes: H01L 23/525 with adaptable interconnections
• CPC Class Codes: H01L 23/5286 Arrangements of power or ground buses
• CPC Class Codes: H01L 23/53238 Additional layers associated with copper layers, e.g. adhesion, barrier, cladding layers
• CPC Class Codes: H01L 23/53295 Stacked insulating layers
• CPC Class Codes: H01L 27/1218 with a particular composition or structure of the substrate
• CPC Class Codes: H01L 27/1225 with semiconductor materials not belonging to the group IV of the periodic table, e.g. InGaZnO
• CPC Class Codes: H01L 27/124 with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits wiring structures per se H01L23/52
• CPC Class Codes: H01L 29/7869 having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
• CPC Class Codes: H03K 17/687 the devices being field-effect transistors

Abstract

The disclosed technology generally relates to integrated circuit (IC), and more particularly to IC devices having one or more power gating switches and methods of fabricating the same. In one aspect, an IC device comprises a front end-of-the-line (FEOL) portion and a back end-of-the-line (BEOL) portion electrically connected to the FEOL portion. The BEOL portion comprises a plurality of metallization levels, wherein each metallization level comprises a plurality of metal lines extending in a lateral direction and a plurality of conductive vertical via structures. The IC device further comprises a power gating transistor formed in the BEOL portion and in direct electrical contact with at least one of the via structures or one of the metal lines.

Claims

1. An integrated circuit (IC) device comprising:

a front end-of-the-line (FEOL) portion;

a back end-of-the-line (BEOL) portion electrically connected to the FEOL portion and comprising a plurality of metallization levels (M_n), wherein each metallization level comprises a plurality of metal lines extending in a lateral direction and a plurality of conductive vertical via structures; and

a power gating transistor formed in the BEOL portion and in direct electrical contact with at least one of the via structures or one of the metal lines.

2. The IC device of claim 1, wherein the power gating transistor comprises a gate electrode, a source electrode and a drain electrode, a channel region and a gate dielectric region, wherein one of the via structures or one of the metal lines serves as the gate electrode and another one of the via structures or one of the metal lines serves as the source electrode or the drain electrode.

3. The IC device of claim 2, wherein the channel region is formed of indium gallium zinc oxide (IGZO).

4. The IC device of claim 2, wherein one of the source electrode or the drain electrode is configured to electrically connect to a power switch and the other of the source electrode or the drain electrode is configured to electrically connect to a portion of the IC device such that the power gating transistor serves as a power switch for delivering power to activate the portion of the IC device when a channel of the power gating transistor is caused to be conduct.

5. The IC device of claim 2, wherein the channel region comprises a planar semiconductor layer and contact the gate dielectric region comprising a planar dielectric layer, the planar semiconductor layer and the planar dielectric layer forming a stack formed vertically between the gate electrode and the source and drain electrodes.

6. The IC device of claim 5, wherein the gate electrode is formed by a metal line in a lower metallization level (M_n), and the source and drain electrodes are formed by conductive vertical via structures in an upper metallization level (M_n+1) disposed over the lower metallization level (M_n) and away from the FEOL.

7. The IC device of claim 5, wherein the source and drain electrodes are formed by a pair of metal lines in a lower metallization level (M_n), and the gate electrode is formed by a conductive vertical via structure in an upper metallization level (M_n+1) disposed over the lower metallization level (M_n) and away from the FEOL.

8. The IC device of claim 1, wherein the power gating transistor comprises:

source and drain electrodes formed by a pair of conductors comprising a lower conductor formed in a lower metallization level (M_n) and an upper conductor formed in an upper metallization level (M_n+1) formed over the lower metallization level (M_n);

a vertically extending channel region having a top end connected to one of the source and drain electrodes and a bottom end connected to another one of the source and drain electrodes, the channel region formed in a via opening above the lower conductor;

a gate dielectric region surrounding the channel region within the via opening; and

a gate electrode in contact with the gate dielectric region and at least partially surrounding the via opening.

9. The IC device of claim 8, wherein the upper conductor is formed at least partially in the via opening.

10. The IC device of claim 8, wherein a metal line in the first metallization level (M_n) serves as the lower conductor.

11. The IC device of claim 1, wherein, wherein the power gating transistor is formed within first three metallization levels (M1, M2, M3) of the IC device.

12. A method of forming an integrated circuit (IC), comprising:

providing a front end-of-line (FEOL) portion;

forming a back end-of-line (BEOL) portion electrically connected to the FEOL portion and comprising a plurality of metallization levels (M_n), wherein each metallization level comprises a plurality of metal lines extending in a lateral direction and a plurality of conductive vertical via structures; and

forming a power gating transistor in the BEOL portion and in direct electrical contact with at least one of the via structures or one of the metal lines.

13. The method of claim 12, wherein forming the power gating transistor comprises electrically connecting one of the via structures or one of the metal lines to a gate dielectric region on a channel region to serve as the gate electrode and electrically connecting another one of the via structures or one of the metal lines to serves as a source electrode or a drain electrode.

14. The method of claim 13, wherein forming the power gating transistor comprises forming the channel region comprising indium gallium zinc oxide (IGZO).

15. The method of claim 14, wherein forming the power gating transistor comprises forming a planar stack of comprising the dielectric region contacting the channel region.

16. The method of claim 15, wherein forming the power gating transistor comprises:

forming the dielectric region over a metal line of a lower metallization level, the metal line serving as the gate electrode; and

forming the channel region on the dielectric region and connecting thereto a pair of vertical via structures of an upper metallization level, the pair serving as the source and drain electrodes of the power gating transistor.

17. The method of claim 16, further comprising an inter-metallization level dielectric layer interposed between the dielectric region and the metal line of a lower metallization level, wherein a combination of the inter-metallization level dielectric and the dielectric region serves as a gate dielectric of the power gating transistor.

18. The method of claim 15, wherein forming the power gating transistor comprises:

forming the channel region on a pair of metal lines of a lower metallization level, the pair serving as the source and drain electrodes; and

forming the dielectric region on the channel region and connecting a vertical via structure of an upper metallization level, the vertical via structure serving as the gate electrode of the power gating transistor.

19. The method of claim 18, further comprising an inter-metallization level dielectric layer interposed between the dielectric region and the vertical via structure of the upper metallization level, wherein a combination of the inter-metallization level dielectric and the dielectric region serves as a gate dielectric of the power gating transistor.

20. The method of claim 14, wherein forming the power gating transistor comprises:

forming a pair of gate dielectric regions separated by a gap and extending in a vertical direction;

after forming the dielectric regions, forming a vertical channel region in the gap such that a bottom end of the vertical channel region contacts a first metal line or a first via structure of a lower metallization level, wherein the metal line serves as one of the source electrode or the drain electrode; and

forming a second metal structure or a second via structure of an upper metallization level, the second metal structure contacting an upper end of the vertical channel region to serve as another one of the source electrode of the drain electrode.