SYSTEMS, CIRCUITS AND METHODS RELATED TO MULTI-MODE POWER AMPLIFIERS HAVING IMPROVED LINEARITY

• US 20150162877A1
• Filed: 11/03/2014
• Published: 06/11/2015
• Est. Priority Date: 11/07/2013
• Status: Active Grant

• Current Assignee: Skyworks Solutions Incorporated
• Original Assignee: Skyworks Solutions Incorporated
• Inventors: NI, Jianxing
• Granted Patent: US 9,467,101 B2
• Time in Patent Office: Days
• US Class Current: 1/1
• CPC Class Codes: H01L 2223/665 Bias feed arrangements
• CPC Class Codes: H01L 2223/6655 Matching arrangements, e.g. arrangement of inductive and capacitive components
• CPC Class Codes: H01L 2224/05554 being square
• CPC Class Codes: H01L 2224/48227 connecting the wire to a bond pad of the item
• CPC Class Codes: H01L 23/66 High-frequency adaptations
• CPC Class Codes: H01L 2924/19105 in a side-by-side arrangement on a common die mounting substrate
• CPC Class Codes: H03F 1/0216 Continuous control
• CPC Class Codes: H03F 1/0261 with control of the polarisation voltage or current, e.g. gliding Class A
• CPC Class Codes: H03F 1/32 Modifications of amplifiers to reduce non-linear distortion by negative feedback H03F1/34
• CPC Class Codes: H03F 1/56 Modifications of input or output impedances, not otherwise provided for
• CPC Class Codes: H03F 2200/18 the bias of the gate of a FET being controlled by a control signal
• CPC Class Codes: H03F 2200/222 A circuit being added at the input of an amplifier to adapt the input impedance of the amplifier
• CPC Class Codes: H03F 2200/318 A matching circuit being used as coupling element between two amplifying stages
• CPC Class Codes: H03F 2200/387 A circuit being added at the output of an amplifier to adapt the output impedance of the amplifier
• CPC Class Codes: H03F 2200/451 the amplifier being a radio frequency amplifier
• CPC Class Codes: H03F 2200/555 A voltage generating circuit being realised for biasing different circuit elements
• CPC Class Codes: H03F 3/19 with semiconductor devices only
• CPC Class Codes: H03F 3/195 in integrated circuits
• CPC Class Codes: H03F 3/21 with semiconductor devices only H03F3/245 takes precedence
• CPC Class Codes: H03F 3/245 with semiconductor devices only
• CPC Class Codes: H04B 1/0475 : with means for limiting noise, interference or distortion H04B1/0483 takes precedence
• CPC Class Codes: H04B 2001/0425 : with linearisation using predistortion

Abstract

Multi-mode power amplifiers (PAs) having improved linearity. A PA can include an amplifying bipolar junction transistor (BJT) configured to receive and amplify a radio-frequency (RF) signal. The PA can further include a biasing circuit configured to provide a first bias signal or a second bias signal to the BJT for operation in a first mode or a second mode. Each of the first bias signal and the second bias signal can be routed to the BJT through a path that includes a common node and a ballast. The PA can further include a linearizing circuit implemented between the common node and a node along an input path for the BJT. The linearizing circuit can be configured as a coupling path to improve linearity of the PA operating in the first mode while allowing the ballast to be sufficiently robust for the PA operating in the second mode.

Claims

1. A power-amplifier (PA) comprising:

a PA circuit that includes a bipolar junction transistor (BJT) having a base, a collector and an emitter, the BJT configured to receive a radio-frequency (RF) signal through an input path and amplify the RF signal;

a biasing circuit in communication with the PA circuit, the biasing circuit configured to provide a first bias signal or a second bias signal to the PA circuit for operation in a first mode or a second mode, respectively, each of the first bias signal and the second bias signal routed to the BJT through a path that includes a common node and a ballast; and

a linearizing circuit implemented between the common node and a node along the input path, the linearizing circuit configured to provide a coupling path between the common node and the input path to improve linearity of the PA circuit operating in the first mode while allowing the ballast to be sufficiently robust for the PA circuit operating in the second mode.

2. The PA of claim 1 wherein the ballast includes a DC ballasting resistance.

3. The PA of claim 1 wherein the BJT includes a heterojunction bipolar transistor (HBT).

4. The PA of claim 1 wherein the BJT is configured such that the RF signal is received at the base through the input path, and the amplified RF signal is output through the collector.

5. The PA of claim 4 wherein the first mode includes an EDGE (enhanced data rates for GSM evolution) mode, and the second mode includes a GPRS (general packet radio service) mode.

6. The PA of claim 5 wherein the biasing circuit includes a current mirror that generates the first bias signal for the operation of the PA circuit in the EDGE mode.

7. The PA of claim 6 wherein the current mirror includes a BJT coupled to a reference current source, the first bias signal being output through an emitter of the BJT to be provided to the common node.

8. The PA of claim 7 wherein the ballast is implemented between the common node and the base of the PA BJT, such that the common node functions as a base-emitter junction between the base of the PA BJT and the emitter of the current mirror BJT.

9. The PA of claim 8 wherein the input path includes a DC blocking capacitance implemented between the base of the PA BJT and a node where the linearizing circuit is connected to.

10. The PA of claim 9 wherein the linearizing circuit is configured to couple the RF signal between the input path and the base-emitter junction to provide rectification on the base-emitter junction and correct AM-AM distortion and thereby yield the improved linearity.

11. The PA of claim 5 wherein the biasing circuit includes a bias resistance implemented between a GPRS bias node and the common node, such that the second bias signal is provided to the gate of the BJT from the GPRS bias node through the bias resistance, the common node, and the ballast.

12. The PA of claim 1 wherein the PA circuit includes a second BJT configured to provide another stage of amplification.

13. The PA of claim 12 wherein the second BJT is implemented so that the input path of the BJT is coupled to an output of the second BJT.

14. The PA of claim 12 wherein the second BJT is configured to receive the amplified RF signal from the BJT.

15. The PA of claim 1 wherein the linearizing circuit includes a capacitance.

16. The PA of claim 15 wherein the capacitance includes a capacitor.

17. The PA of claim 15 wherein the linearizing circuit further includes a resistance connected in series with the capacitance.

18. The PA of claim 15 wherein the linearizing circuit further includes an inductance connected in series with the capacitance.

19. A power-amplifier (PA) module comprising:

a packaging substrate configured to receive a plurality of components;

a power amplifier (PA) circuit formed on a die that is mounted on the packaging substrate, the PA circuit including a bipolar junction transistor (BJT) having a base, a collector and an emitter, the BJT configured to receive a radio-frequency (RF) signal through an input path and amplify the RF signal;

a biasing circuit in communication with the PA circuit, the biasing circuit configured to provide a first bias signal or a second bias signal to the PA circuit for operation in a first mode or a second mode, respectively, each of the first bias signal and the second bias signal routed to the BJT through a path that includes a common node and a ballast; and

a linearizing circuit implemented between the common node and a node along the input path, the linearizing circuit configured to provide a coupling path between the common node and the input path to improve linearity of the PA circuit operating in the first mode while allowing the ballast to be sufficiently robust for the PA circuit operating in the second mode.

20. A method for operating a power-amplifier (PA), the method comprising:

receiving a radio-frequency (RF) signal through an input path in a PA circuit that includes a bipolar junction transistor (BJT) having a base, a collector and an emitter;

providing a first bias signal or a second bias signal to the PA circuit for operation in a first mode or a second mode, respectively, each of the first bias signal and the second bias signal routed to the BJT through a path that includes a common node and a ballast; and

coupling the common node and a node along the input path with a linearizing circuit to improve linearity of the PA circuit operating in the first mode while allowing the ballast to be sufficiently robust for the PA circuit operating in the second mode.