CLOCK GENERATION CIRCUIT

• US 20150162917A1
• Filed: 11/12/2014
• Published: 06/11/2015
• Est. Priority Date: 12/10/2013
• Status: Active Grant

• Current Assignee: Sony Semiconductor Solutions Corporation (Sony Group Corp.)
• Original Assignee: Sony Corporation (Sony Group Corp.)
• Inventors: Tsukuda, Yasunori
• Granted Patent: US 9,484,948 B2
• Time in Patent Office: Days
• US Class Current: 1/1
• CPC Class Codes: H03K 21/02 Input circuits
• CPC Class Codes: H03K 21/023 comprising pulse shaping or differentiating circuits
• CPC Class Codes: H03L 7/197 a time difference being used for locking the loop, the counter counting between numbers which are variable in time or the frequency divider dividing by a factor variable in time, e.g. for obtaining fractional frequency division H03L7/1806 takes precedence
• CPC Class Codes: H03M 3/30 Delta-sigma modulation

Abstract

The present technique relates to a clock generation circuit including a phase difference comparison circuit configured to compare a phase of each of an input clock signal and a feedback signal, and provides a phase difference signal indicating a phase difference between the input clock signal and the feedback signal, a filter circuit configured to suppress a high frequency component in the phase difference signal, an output circuit configured to modulate the phase difference signal in such a manner as to decrease a noise component of a low frequency band and increase a noise component of a high frequency band, and generate and output an output clock signal from the modulated phase difference signal and a reference clock signal, and a frequency dividing circuit configured to divide a frequency of the output clock signal, at a predetermined frequency dividing ratio, and feed it back to the phase comparison circuit.

Claims

1. A clock generation circuit comprising:

a phase difference comparison circuit configured to compare a phase of each of an input clock signal and a feedback signal which have been received, and provides a phase difference signal indicating a phase difference between the input clock signal and the feedback signal;

a filter circuit configured to suppress a high frequency component, of which frequency is higher than a predetermined cutoff frequency, in the phase difference signal;

an output circuit configured to modulate the phase difference signal, of which high frequency component is suppressed, in such a manner as to decrease a noise component of a low frequency band and increase a noise component of a high frequency band, and generate and output an output clock signal from the modulated phase difference signal and a reference clock signal; and

a frequency dividing circuit configured to divide a frequency of the output clock signal, which has been output, at a predetermined frequency dividing ratio, and feed the output clock signal back to the phase comparison circuit as the feedback signal.

2. The clock generation circuit according to claim 1, wherein the output circuit includes:

a modulator configured to modulate the phase difference signal of which high frequency component has been suppressed; and

a multiplier circuit configured to multiply the reference clock signal by a multiplication ratio according to the phase difference indicated by the frequency dividing ratio setting signal which has been modulated, and output the output clock signal.

3. The clock generation circuit according to claim 2, wherein the output circuit further includes an adjustment unit configured to adjust the phase difference indicated by the phase difference signal so that it attains a value obtained by multiplying a ratio of a frequency of the reference clock signal with respect to a frequency of the input clock signal by the predetermined frequency dividing ratio, and input the phase difference signal indicating the adjusted value into the modulator.

4. The clock generation circuit according to claim 3, wherein the multiplier circuit includes:

a phase difference detector configured to compare phases of the reference clock signal and an internal signal, and detect a phase difference between the reference clock signal and the internal signal;

an oscillator configured to oscillate at a frequency according to the phase difference detected by the phase difference detector, and generate the output clock signal; and

a variable frequency divider configured to divide a frequency of the output clock signal, which has been generated, at a frequency dividing ratio equal to the value indicated by the phase difference signal which has been modulated, and feed the output clock signal back to the phase difference detector as the internal signal.

5. The clock generation circuit according to claim 1 further comprising a detection circuit configured to provide the phase comparison circuit with a detection result obtained by detecting an edge of the input clock signal on the basis of a clock signal of a frequency higher than the input clock signal.

6. The clock generation circuit according to claim 5, wherein the detection circuit detects an edge of the input clock signal on the basis of the output clock signal.

7. The clock generation circuit according to claim 1, wherein the modulation performed on the phase difference signal is sigma delta modulation.

8. An electronic device comprising:

a reference clock providing circuit configured to provide a predetermined reference clock signal;

a phase difference comparison circuit configured to compare a phase of each of an input clock signal and a feedback signal which have been input, and provides a phase difference signal indicating a phase difference between the input clock signal and the feedback signal;

a filter circuit configured to suppress a high frequency component, of which frequency is higher than a predetermined cutoff frequency, in the phase difference signal;

an output circuit configured to modulate the phase difference signal, of which high frequency component is suppressed, in such a manner as to decrease a noise component of a low frequency band and increase a noise component of a high frequency band, and generate and output an output clock signal from the modulated phase difference signal and a reference clock signal; and

a frequency dividing circuit configured to divide a frequency of the output clock signal, which has been output, at a predetermined frequency dividing ratio, and feed the output clock signal back to the phase comparison circuit as the feedback signal.