BIMODAL SERIAL LINK CDR ARCHITECTURE

• US 20150162922A1
• Filed: 11/21/2014
• Published: 06/11/2015
• Est. Priority Date: 12/05/2013
• Status: Active Grant

• Current Assignee: Samsung Display Company Limited (Samsung Electronics Co. Ltd.)
• Original Assignee: Samsung Display Company Limited (Samsung Electronics Co. Ltd.)
• Inventors: Amirkhany, Amir, Song, Sanquan
• Granted Patent: US 9,312,865 B2
• Time in Patent Office: Days
• US Class Current: 1/1
• CPC Class Codes: G09G 5/008 Clock recovery
• CPC Class Codes: H03L 7/07 using several loops, e.g. for redundant clock signal generation
• CPC Class Codes: H03L 7/0807 concerning mainly a recovery circuit for the reference signal
• CPC Class Codes: H03L 7/087 using at least two phase detectors or a frequency and phase detector in the loop
• CPC Class Codes: H03L 7/0891 the up-down pulses controlling source and sink current generators, e.g. a charge pump
• CPC Class Codes: H03L 7/091 the phase or frequency detector using a sampling device H03L7/087 takes precedence
• CPC Class Codes: H03L 7/1072 by changing characteristics of the charge pump, e.g. changing the gain
• CPC Class Codes: H03L 7/145 the switched reference signal being derived from the controlled oscillator output signal
• CPC Class Codes: H04L 7/0008 Synchronisation information channels, e.g. clock distribution lines
• CPC Class Codes: H04L 7/0025 interpolation of clock signal
• CPC Class Codes: H04L 7/0091 Transmitter details
• CPC Class Codes: H04L 7/033 using the transitions of the received signal to control the phase of the synchronising-signal-generating means, e.g. using a phase-locked loop
• CPC Class Codes: H04L 7/0331 with a digital phase-locked loop [PLL] processing binary samples, e.g. add/subtract logic for correction of receiver clock H04L7/0337 takes precedence

Abstract

A system for generating a local clock, configurable to utilize a forwarded clock and a data stream, or a data stream only, as frequency and phase references. In one embodiment, the system includes a phase locked loop that may be referenced to a forwarded clock, or to a phase reference formed from received data, utilizing a sampler, a crossing sampler, and a bang-bang phase detector. The system includes a local phase recovery loop which may utilize the bang-bang phase detector as part of a phase detector for controlling a phase interpolator, the output of the phase interpolator serving as the local clock for clocking received data.

Claims

1. A system for generating a local clock, the system comprising:

a controlled oscillator having an input and an output;

a first link data input;

a forwarded clock input; and

a first phase detector having a first input, a second input, and an output; and

a first phase recovery block having a clock input, a data input connected to the first link data input, and an output switch-connected to the input of the controlled oscillator;

the first input of the first phase detector being connected to the output of the controlled oscillator,

the second input of the first phase detector being connected to the forwarded clock input, and

the output of the first phase detector being switch-connected to the controlled oscillator.

2. The system of claim 1, further comprising a charge pump and an analog loop filter, the charge pump and the analog loop filter connected in cascade between the output of the first phase detector and the input of the controlled oscillator.

3. The system of claim 1, further comprising a first phase interpolator having:

an oscillator input;

a phase adjust input; and

an output;

the oscillator input of the first phase interpolator being connected to the output of the controlled oscillator and the output of the first phase interpolator being connected to the clock input of the first phase recovery block.

4. The system of claim 3 further comprising:

a second link data input;

a second phase recovery block having a clock input, a data input, and an output, the data input of the second phase recovery block being connected to the second link data input;

a second phase interpolator having an oscillator input, a phase adjust input, and an output;

the output of the second phase recovery block being connected to the phase adjust input of the second phase interpolator,

the oscillator input of the second phase interpolator being connected to the output of the controlled oscillator, and

the output of the second phase interpolator being connected to the clock input of the second phase recovery block.

5. The system of claim 3, further comprising a divider having an input and an output, the input of the divider connected to an output of the controlled oscillator and the output of the divider being connected to the first input of the first phase detector.

6. The system of claim 5, wherein the first phase detector is a linear phase detector comprising a circuit to generate an analog output signal proportional to the difference in phase between a signal at the first input of the first phase detector and a signal at the second input of the first phase detector.

7. The system of claim 6, wherein the first phase interpolator comprises:

a circuit to generate, at the output of the first phase interpolator, a signal differing in phase from a signal at the oscillator input of the first phase interpolator, by an amount corresponding to a signal at the phase adjust input of the first phase interpolator.

8. The system of claim 7, further comprising a digital loop filter comprising:

an input;

an output; and

a circuit to receive, at the input of the digital loop filter, a digital input signal, and to generate, at the output of the loop filter, a digital output signal.

9. The system of claim 8, wherein the first phase recovery block comprises:

a first sampler;

a second sampler;

each of the first sampler of the first phase recovery block and the second sampler of the first phase recovery block comprising;

a data input,

a clock input, and

an output; and

a bang-bang phase detector comprising a first input, a second input, and an output.

10. The system of claim 9, wherein:

the clock input of the first sampler and the clock input of the second sampler are connected to the clock input of the first phase recovery block;

the data input of the first sampler and the data input of the second sampler are connected to the data input of the first phase recovery block;

the output of the first sampler is connected to the first input of the bang-bang phase detector;

the output of the second sampler is connected to the second input of the bang-bang phase detector; and

the output of the bang-bang phase detector is connected to the output of the first phase recovery block.

11. The system of claim 3, further comprising a control logic circuit to select between a first mode of operation and a tracking phase of a second mode of operation, wherein

in the first mode of operation, the output of the first phase detector is connected, with an enabled connection, to the input of the controlled oscillator, and

in the tracking phase of the second mode of operation, the output of the first phase recovery block is connected, with an enabled connection, to the input of the controlled oscillator.

12. The system of claim 11, wherein, in the first mode of operation, the output of the first phase recovery block is connected, with an enabled connection, to the phase adjust input of the first phase interpolator.

13. The system of claim 11, wherein the control logic circuit further is a circuit to select between the first mode of operation, the tracking phase of the second mode of operation, and a training phase of the second mode of operation, wherein, in the training phase of the second mode of operation, the output of the first phase detector is connected, with an enabled connection, to the input of the controlled oscillator, and the first link data input is connected, with an enabled connection, to the forwarded clock input.

14. The system of claim 13, further comprising a transmitter, the transmitter comprising a circuit to, in the training phase of the second mode of operation, transmit a pattern of alternating groups of ones and zeros.

15. The system of claim 11, further comprising:

a data buffer comprising an output and a differential input, the differential input comprising a first conductor and a second conductor;

a forwarded clock buffer comprising an output and a differential input, the differential input comprising a first conductor and a second conductor;

wherein the control logic circuit further is a circuit to select between the first mode of operation, the tracking phase of the second mode of operation, and a training phase of the second mode of operation,

wherein, in the training phase of the second mode of operation;

the output of the first phase detector is connected, with an enabled connection, to the input of the controlled oscillator,

the first conductor of the differential input of the data buffer is connected, with an enabled connection, to the first conductor of the differential input of the forwarded clock buffer, and

the second conductor of the differential input of the data buffer is connected, with an enabled connection, to the second conductor of the differential input of the forwarded clock buffer.

16. A display, comprising:

a timing controller;

a driver integrated circuit (IC); and

a serial data link connecting the timing controller and the driver IC,

the driver IC comprising the system of claim 1.

17. The display of claim 16, wherein the display is an organic light emitting diode (OLED) display or a liquid crystal display (LCD).