SATELLITE SIGNAL FREQUENCY TRANSLATION AND STACKING

• US 20150162998A1
• Filed: 08/04/2014
• Published: 06/11/2015
• Est. Priority Date: 11/03/2006
• Status: Active Grant

• Current Assignee: Entropic Communications, LLC (FIG LLC (d/b/a Fortress Investment Group LLC))
• Original Assignee: Entropic Communications Incorporated (Maxlinear Incorporated)
• Inventors: Petrovic, Branislav A., Hancock, Dale, Goldblatt, Jeremy, Bargroff, Keith
• Granted Patent: US 9,413,476 B2
• Time in Patent Office: Days
• US Class Current: 1/1
• CPC Class Codes: H04B 1/16 Circuits
• CPC Class Codes: H04B 1/28 the receiver comprising at least one semiconductor device having three or more electrodes
• CPC Class Codes: H04H 40/90 specially adapted for satellite broadcast receiving

Abstract

An outdoor satellite receiving unit (ODU) receives several independent satellite signals, selects two signals with a switch matrix, downconverts the two signals to a bandstacked signal with a high and a low band signal, and outputs the bandstacked signal on the same cable to receiver units. Several satellite signals can be selected in groups of two or more and output to independent receiver units. Signal selecting is performed at the received radio frequency (RF) and bandstacking is performed with a single downconversion step to an intermediate frequency (IF). Channel stacking on the same cable of more than two channels from several satellites can be achieved by using frequency agile downconverters and bandpass filters prior to combining at the IF output. A slow transitioning switch minimizes signal disturbances when switching and maintains input impedance at a constant value.

Claims

1. A switch element, comprising:

an input port;

an output port;

an internal termination having an impedance of Z;

a first switch component having first variable impedance Z₁ coupled between the input port and the internal termination; and

a second switch component having second variable impedance Z₂ coupled between the input port and the output port;

wherein a means for controlling impedance controls the impedance of both the first switch component and the second switch component to maintain a substantially constant input impedance.

2. The switch element of claim 1, wherein the switch element is a single pole double throw (SPDT) switch element.

3. The switch element of claim 1, wherein the input impedance is substantially constant when the switch element is any state, including ON, OFF, and in transition.

4. The switch element of claim 3, wherein the means of controlling impedance is a switch control circuit, wherein the switch control circuit generates a time varying control signal having a controllable rate of change to control the impedances Z₁ and Z₂ at a given time.

5. The switch element of claim 4, wherein the impedance relationship substantially achieved by the switch control circuit is described by the equation Z₁·

Z₂=Z² and wherein the substantially constant input impedance has an impedance of Z.

6. The switch element of claim 5, wherein the switch control circuit causes the impedance Z₁ to linearly change with time when the switch element is in transition.

7. The switch element of claim 6, wherein the switch control circuit causes the impedance Z₂ to hyperbolically change with time when the switch element is in transition.

8. The switch element of claim 5, wherein the first switch component is a first field-effect transistor (FET) switch and wherein the second switch component is a second FET switch.

9. The switch element of claim 8, wherein the switch control circuit comprises:

a first digital to analog converter (DAC) coupled to the first FET switch and configured to generate a voltage to control the impedance Z₁ of the first FET switch as a function of time; and

a second DAC coupled to the second FET switch and configured to generate a voltage to control the impedance Z₂ of the second FET switch as a function of time.

10. The switch element of claim 8, wherein the switch control circuit comprises a linearized transconductance circuit driven by differential sweep signals when the switch element transitions, wherein the differential sweep signals generate complementary control voltages VDCM and VDCP configured to drive the first FET switch and the second FET switch, respectively.

11. A system, comprising:

a switch element, comprising;

an input port;

an output port;

an internal termination having an impedance Z;

a first switch component having first variable impedance Z₁ coupled between the input port and the internal termination; and

a second switch component having second variable impedance Z₂ coupled between the input port and the output port; and

a means for controlling the impedance of both the first switch component and the second switch component to maintain a substantially constant input impedance.

12. The system of claim 11, wherein the switch element is a single pole double throw (SPDT) switch element.

13. The system of claim 11, wherein the input impedance is substantially constant when the switch element is any state, including ON, OFF and in transition.

14. The system of claim 13, wherein the means of controlling impedance is a switch control circuit, wherein the switch control circuit generates a time varying control signal having a controllable rate of change to control the impedances Z₁ and Z₂ at a given time.

15. The system of claim 14, wherein the impedance relationship substantially achieved by the switch control circuit is described by the equation Z₁·

Z₂=Z² and wherein the substantially constant input impedance has an impedance of Z.

16. The system of claim 15, wherein the switch control circuit causes the impedance Z₁ to linearly change with time when the switch element is in transition.

17. The system of claim 16, wherein the switch control circuit causes the impedance Z₂ to hyperbolically change with time when the switch element is in transition.

18. The system of claim 15, wherein the first switch component is a first field-effect transistor (FET) switch and wherein the second switch component is a second FET switch.

19. The system of claim 18, wherein the switch control circuit comprises:

a first digital to analog converter (DAC) coupled to the first FET switch and configured to generate a voltage to control the impedance Z₁ of the first FET switch as a function of time; and

a second DAC coupled to the second FET switch and configured to generate a voltage to control the impedance Z₂ of the second FET switch as a function of time.

20. The system of claim 18, wherein the switch control circuit comprises a linearized transconductance circuit driven by differential sweep signals when the switch element transitions, wherein the differential sweep signals generate complementary control voltages VDCM and VDCP configured to drive the first FET switch and the second FET switch, respectively.