Runtime Optimization of Multi-core System Designs for Increased Operating Life and Maximized Performance

• US 20150169363A1
• Filed: 12/08/2014
• Published: 06/18/2015
• Est. Priority Date: 12/18/2013
• Status: Abandoned Application

• Current Assignee: Qualcomm, Inc.
• Original Assignee: Qualcomm, Inc.
• Inventors: Anderson, Jon James, Stewart, Richard Alan
• Application Number:
  US14/563,333
• Publication Number:
  US 20150169363A1
• Time in Patent Office: Days
• US Class Current: 1/1
• CPC Class Codes: G06F 9/4818 Priority circuits therefor
• CPC Class Codes: G06F 9/4881 Scheduling strategies for dispatcher, e.g. round robin, multi-level priority queues
• CPC Class Codes: G06F 9/4893 taking into account power or heat criteria power management in computers in general G06F1/3203; thermal management in computers in general G06F1/206
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

Aspects include computing devices, systems, and methods for adjusting the assignment of tasks to processor cores in a multi-core processing system. In an aspect, a reliability engine may be configured to determine priorities for a selected cluster of processor cores according to various methods depending on whether the selected processor cores are inactive and/or whether the computing device is in a cold boot state. The reliability engine may be configured to determine the priorities according to a round robin scheme, a pseudorandom scheme, from stored and/or collected operation data, or from stored and/or collected built in self test data in response to various activities and boot states of the processor cores. The reliability engine may rearrange a virtual processor identification translation table according to the priorities of the equivalent processor cores.

Claims

1. A method of assigning processing tasks to processor cores within a multi-core processor of a computing device in order to extend an operating life of the multi-core processor, comprising:

selecting a plurality of processor cores;

determining whether the computing device is in a cold boot state;

determining a priority for each of the plurality of processor cores in response to determining that the computing device is in a cold boot state; and

assigning processor requests to specific processor cores of the plurality of processor cores based on the determined priority for each of the plurality of processor cores.

2. The method of claim 1, wherein determining a priority for each of the plurality processor cores comprises:

retrieving a previous priority for each of the plurality of processor cores from a non-volatile memory; and

modifying the previous priority for each of the plurality of processor cores using a round robin scheme.

3. The method of claim 2, wherein modifying the previous priority for each of the plurality of processor cores using a round robin scheme comprises shifting the previous priority for each of the plurality of processor cores by an amount such that that the determined priority for each of the plurality of processor cores is different from the previously stored priority for each of the plurality of processor cores.

4. The method of claim 1, wherein determining a priority for each of the plurality of processor cores comprises assigning a priority to each of the plurality of processor cores using a pseudorandom scheme.

5. The method of claim 4, wherein assigning a priority to each of the plurality of processor cores using a pseudorandom scheme comprises selecting a priority for each of the plurality of processor cores from a set of priorities such that each of the plurality of processor cores is assigned a different priority.

6. The method of claim 1, further comprising:

determining whether each of the plurality of processor cores is inactive, wherein determining a priority for each of the plurality of processor cores in response to determining that the computing device is in a cold boot state comprises determining a priority for each of the plurality of processor cores in response to determining that the computing device is in a cold boot state and that each of the plurality of processor cores is inactive; and

storing the determined priority for each of the plurality of processor cores in a non-volatile memory.

7. The method of claim 6, further comprising:

in response to determining that at least one of the plurality of processor cores is active;

obtaining information relevant to wear out regarding each of the processor cores within the multi-core processor by measuring one or more of a temperature, cumulative usage, and a current leakage of the processor cores under normal operations; and

determining a priority for each of the processor cores based on the obtained information relevant to wear out; and

in response to determining that each of the plurality of processor cores are inactive and that that the computing device is not in a cold boot state;

providing a test workload to each of the processor cores;

collecting test data by measuring one or more of thermal output and current leakage of the processor cores under the test workload individually or for groups of the processor cores in response to providing the test workload;

retrieving historical operating time for each of the processor cores; and

determining a priority for each of the processor cores based on the collected test data and historical operating time.

8. The method of claim 1, further comprising:

detecting degradation of performance or lifetime of each of the plurality of processor cores;

determining whether any processor core detected to have degraded performance or lifetime has failed or is inefficient;

assigning any processor core determined to be inefficient a priority that will not be executed;

removing any processor core determined to have failed from a pool from which processor cores are selected; and

updating the priority of any processor core detected to have degraded performance or lifetime.

9. A computing device, comprising a multi-core processor having multiple processor cores, wherein the multi-core processor is configured with processor-executable instructions to perform operations comprising:

selecting a plurality of processor cores;

determining whether the computing device is in a cold boot state;

determining a priority for each of the plurality of processor cores in response to determining that the computing device is in a cold boot state; and

assigning processor requests to specific processor cores of the plurality of processor cores based on the determined priority for each of the plurality of processor cores.

10. The computing device of claim 9, wherein the multi-core processor is configured with processor-executable instructions to perform operations such that determining a priority for each of the plurality processor cores comprises:

retrieving a previous priority for each of the plurality of processor cores from a non-volatile memory; and

modifying the previous priority for each of the plurality of processor cores using a round robin scheme.

11. The computing device of claim 10, wherein the multi-core processor is configured with processor-executable instructions to perform operations such that modifying the previous priority for each of the plurality of processor cores using a round robin scheme comprises shifting the previous priority for each of the plurality of processor cores by an amount such that that the determined priority for each of the plurality of processor cores is different from the previously stored priority for each of the plurality of processor cores.

12. The computing device of claim 9, wherein the multi-core processor is configured with processor-executable instructions to perform operations such that determining a priority for each of the plurality of processor cores comprises assigning a priority to each of the plurality of processor cores using a pseudorandom scheme.

13. The computing device of claim 12, wherein the multi-core processor is configured with processor-executable instructions to perform operations such that assigning a priority to each of the plurality of processor cores using a pseudorandom scheme comprises selecting a priority for each of the plurality of processor cores from a set of priorities such that each of the plurality of processor cores is assigned a different priority.

14. The computing device of claim 9, wherein the multi-core processor is configured with processor-executable instructions to perform operations further comprising:

determining whether each of the plurality of processor cores is inactive, wherein determining a priority for each of the plurality of processor cores in response to determining that the computing device is in a cold boot state comprises determining a priority for each of the plurality of processor cores in response to determining that the computing device is in a cold boot state and that each of the plurality of processor cores is inactive; and

storing the determined priority for each of the plurality of processor cores in a non-volatile memory.

15. The computing device of claim 14, wherein the multi-core processor is configured with processor-executable instructions to perform operations further comprising:

in response to determining that at least one of the plurality of processor cores is active;

obtaining information relevant to wear out regarding each of the processor cores within the multi-core processor by measuring one or more of a temperature, cumulative usage, and a current leakage of the processor cores under normal operations; and

determining a priority for each of the processor cores based on the obtained information relevant to wear out; and

in response to determining that each of the plurality of processor cores are inactive and that that the computing device is not in a cold boot state;

providing a test workload to each of the processor cores;

collecting test data by measuring one or more of thermal output and current leakage of the processor cores under the test workload individually or for groups of the processor cores in response to providing the test workload;

retrieving historical operating time for each of the processor cores; and

determining a priority for each of the processor cores based on the collected test data and historical operating time.

16. The computing device of claim 9, wherein the multi-core processor is configured with processor-executable instructions to perform operations further comprising:

detecting degradation of performance or lifetime of each of the plurality of processor cores;

determining whether any processor core detected to have degraded performance or lifetime has failed or is inefficient;

assigning any processor core determined to be inefficient a priority that will not be executed;

removing any processor core determined to have failed from a pool from which processor cores are selected; and

updating the priority of any processor core detected to have degraded performance or lifetime.

17. A non-transitory processor-readable medium having stored thereon processor-executable instructions configured to cause a multi-core processor of a computing device to perform operations comprising:

selecting a plurality of processor cores;

determining whether the computing device is in a cold boot state;

determining a priority for each of the plurality of processor cores in response to determining that the computing device is in a cold boot state; and

assigning processor requests to specific processor cores of the plurality of processor cores based on the determined priority for each of the plurality of processor cores.

18. The non-transitory processor-readable medium of claim 17, wherein the stored processor-executable instructions are configured to cause the multi-core processor to perform operations such that determining a priority for each of the plurality processor cores comprises:

retrieving a previous priority for each of the plurality of processor cores from a non-volatile memory; and

modifying the previous priority for each of the plurality of processor cores using a round robin scheme.

19. The non-transitory processor-readable medium of claim 17, wherein the stored processor-executable instructions are configured to cause the multi-core processor to perform operations such that determining a priority for each of the plurality processor cores comprises assigning a priority to each of the plurality of processor cores using a pseudorandom scheme.

20. The non-transitory processor-readable medium of claim 17, wherein the stored processor-executable instructions are configured to cause the multi-core processor to perform operations further comprising:

determining whether each of the plurality of processor cores is inactive, wherein determining a priority for each of the plurality of processor cores in response to determining that the computing device is in a cold boot state comprises determining a priority for each of the plurality of processor cores in response to determining that the computing device is in a cold boot state and that each of the plurality of processor cores is inactive; and

storing the determined priority for each of the plurality of processor cores in a non-volatile memory.