INTEGRATED CIRCUIT PACKAGE AND METHOD

• US 20150169817A1
• Filed: 04/10/2014
• Published: 06/18/2015
• Est. Priority Date: 12/18/2013
• Status: Active Grant

• Current Assignee: NXP B.V. (NXP Semiconductors NV)
• Original Assignee: NXP B.V. (NXP Semiconductors NV)
• Inventors: Spehar, James, Kim, Jong, Zhang, Xu
• Granted Patent: US 9,430,604 B2
• Time in Patent Office: Days
• US Class Current: 1/1
• CPC Class Codes: G06F 2113/18 Chip packaging
• CPC Class Codes: G06F 30/367 Design verification, e.g. using simulation, simulation program with integrated circuit emphasis [SPICE], direct methods or relaxation methods
• CPC Class Codes: G06F 30/392 Floor-planning or layout, e.g. partitioning or placement
• CPC Class Codes: G06F 30/394 Routing G06F30/396 takes precedence
• CPC Class Codes: H01L 23/64 Impedance arrangements
• CPC Class Codes: H01L 25/0655 the devices being arranged next to each other
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

Various example embodiments are directed to methods and apparatuses for implementing a circuit design within an integrated circuit (IC) package. A respective capacitance is determined for each die contact of a circuit design. A respective target inductance range is selected for each of the plurality of die contacts based on the determined capacitance. A segmentation of the circuit design is determined as a function of the target inductance ranges. The segmentation defines an implementation of the circuit design on a plurality of IC dies. The IC dies are placed at respective locations on the substrate, based on the resulting inductances of connections (e.g., conductive traces) between the die contacts and terminals of the IC package.

Claims

1. A method for implementing a circuit design within an integrated circuit (IC) package having substrate and terminals for carrying signals communicated by the circuits of the circuit design, the method comprising:

determining a respective capacitance of each die contact of a plurality of die contacts of a circuit design;

selecting a respective target inductance range for each of the plurality of die contacts based on the determined capacitance of the die contact;

determining as a function of the target inductance ranges, a segmentation of the circuit design that defines at least a first IC die and a second IC die; and

placing the first and second IC dies at respective locations on the substrate, at which the inductance of each connection, from the plurality of die contacts to terminals of the IC package, is within the target inductance range of the corresponding die contact.

2. The method of claim 1, wherein the selecting of the target inductance range for each die contact includes, for each die contact of the plurality of die contacts, selecting the respective target inductance range based on the determined capacitance and a respective frequency response parameter.

3. The method of claim 2, wherein the determining of the respective capacitance of each die contact of the plurality of die contacts includes simulating the circuit design.

4. The method of claim 2, further comprising:

simulating the circuit design to determine a respective highest frequency of signals carried by each of the plurality of die contacts; and

for each of the plurality of die contacts, determining the respective frequency response parameter based on the respective highest frequency.

5. The method of claim 2, further comprising:

retrieving the frequency response parameter for each of the plurality of die contacts from a package model specification.

6. The method of claim 1, wherein the connections between the plurality of die contacts and the terminals of the IC package are conductive traces on the substrate.

7. The method of claim 1, further comprising:

routing each connection, from the plurality of die contacts to terminals of the IC package, to have a length causing the connection to have an inductance within the target inductance range of the corresponding die contact.

8. The method of claim 1, wherein the selecting of the target inductance range for each die contact includes, for each die contact of the plurality of die contacts, selecting the respective target inductance range based on the determined capacitance and a respective delay or skew parameter.

9. A method for implementing a circuit design within an integrated circuit (IC) package having a substrate, the package supporting first terminals for carrying high-bandwidth signals and supporting a given plurality of second terminals for carrying low-bandwidth signals, the method comprising:

determining a respective capacitance of each of a plurality of die contacts of the circuit design;

selecting a respective target inductance range for each of the plurality of die contacts based on the determined capacitance of the die contact;

assigning an initial segmentation of the circuit design defining an initial first IC die and an initial second IC die;

assigning an initial first location for the first IC die on the substrate and an initial second location for the second IC die on the substrate;

for each connection from one of the plurality of the die contacts of the circuit design to a respective terminal of the IC package, calculating a characteristic inductance for the connection; and

in response to the calculated characteristic inductance falling outside the target inductance range, laterally displacing at least one of the first and second IC dies on the substrate as a function of the calculated characteristic inductance.

10. The method of claim 9, wherein the selecting of the target inductance range for each die contact includes, for each die contact the plurality of die contacts, selecting the respective target inductance range based on the determined capacitance and a respective frequency response parameter.

11. The method of claim 10, wherein the determining of the respective capacitance of each die contact of the plurality of die contacts includes simulating the circuit design.

12. The method of claim 10, further comprising:

simulating the circuit design to determine a respective highest frequency of signals carried by each of the plurality of die contacts; and

for each of the plurality of die contacts, determining the respective frequency response parameter based on the respective highest frequency.

13. The method of claim 10, further comprising:

retrieving the frequency response parameter for each of the plurality of die contacts from a package model specification.

14. The method of claim 9, in further response to the calculated characteristic inductance falling outside the target inductance range, repeating the calculating and laterally displacing steps until either of the following conditions is detected:

(i) the characteristic inductances are within the target inductance ranges, or

(ii) the target inductance ranges cannot be met using the initial segmentation.

15. The method of claim 14, further comprising in response to determining that the target inductance ranges cannot be met using the initial segmentation, assigning a second segmentation of the circuit design that is different from the initial segmentation.

16. The method of claim 9, wherein the calculating the of the characteristic inductance, for a connection from one of the plurality of the die contacts to a respective terminal of the IC package, calculates the inductance based on a shortest length connection between the one of the plurality of die contracts and the respective terminal.

17. The method of claim 9, wherein the connections, from the plurality of die contacts to terminals of the IC package, are conductive traces on the substrate.

18. The method of claim 9, further comprising routing each connection, from the plurality of die contacts to terminals of the IC package, to have a length causing the connection to have an inductance within the target inductance range of the corresponding die contact.

19. An integrated circuit (IC) package, comprising,

a plurality of terminals;

a substrate;

a plurality of IC dies placed on the substrate, the plurality of IC dies including a plurality of die contacts, and each IC die including a respective sub-circuit of a communication circuit configured to communicate data signals at a target frequency via the die contacts;

a set of conductive traces, each connecting a respective one of the plurality of die contacts to a respective one of the terminals of the IC package; and

wherein the IC dies are placed at locations on the substrate at which each conductive trace of the set, the respective die contact and respective terminal connected thereto together exhibit a frequency response that does not attenuate frequencies at or below the target frequency.

20. The IC package of claim 19, wherein the target frequency is greater than or equal to 2 GHz.