DESIGN RULE CHECKING FOR CONFINING WAVEFORM INDUCED CONSTRAINT VARIATION IN STATIC TIMING ANALYSIS

• US 20150169819A1
• Filed: 05/09/2014
• Published: 06/18/2015
• Est. Priority Date: 12/13/2013
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: HSU, Meng-Kai, CHEN, Wen-Hao
• Granted Patent: US 9,165,105 B2
• Time in Patent Office: Days
• US Class Current: 1/1
• CPC Class Codes: G06F 2119/12 Timing analysis or timing optimisation
• CPC Class Codes: G06F 30/367 Design verification, e.g. using simulation, simulation program with integrated circuit emphasis [SPICE], direct methods or relaxation methods
• CPC Class Codes: G06F 30/398 Design verification or optimisation, e.g. using design rule check [DRC], layout versus schematics [LVS] or finite element methods [FEM] optical proximity correction [OPC] design processes G03F1/36

Abstract

A method for design rule checking (DRC) during static timing analysis (STA) of an integrated circuit (IC) design comprises analyzing cells with distorted waveforms in a cell library and generating both library-based and simulated waveforms for each cell type according to a plurality of parameters for the cell type. The method further comprises constructing a lookup table based on analysis of the distorted waveforms, wherein the lookup table maps waveform error to hold time constraint error of each cell type in the library. The method further comprises identifying one or more cells in the IC design as risky for timing constraint violation during static timing analysis of the IC design according to the lookup table and re-optimizing the identified risky cells to reduce risk for timing violation of the IC design.

Claims

1. A computer-implemented method for design rule checking (DRC) during static timing analysis (STA) of an integrated circuit (IC) design, comprising:

analyzing cells with distorted waveforms in a cell library and generating both library-based and simulated waveforms for each cell type according to a plurality of parameters for the cell type;

constructing a lookup table based on analysis of the distorted waveforms, wherein the lookup table maps waveform error to hold time constraint error of each cell type in the library and is saved in a memory;

identifying one or more cells in the IC design as risky for timing constraint violation during static timing analysis of the IC design according to the lookup table;

re-optimizing the identified risky cells to reduce risk for timing violation of the IC design.

2. The computer-implemented method of claim 1, wherein:

the plurality of parameters for the cell type include process, voltage, and temperature (PVT) set during fabrication, cell type, input slew, and output loading of the cell type.

3. The computer-implemented method of claim 1, further comprising:

distorting the waveforms by one or more of distortion delay and starting voltage of waveform distortion.

4. The computer-implemented method of claim 1, further comprising:

measuring the waveform error as an enclosed area between the library-based and simulated waveforms of the cell type.

5. The computer-implemented method of claim 1, further comprising:

establishing a relationship between the waveform error and the constraint error of the cell type via linear regression.

6. The computer-implemented method of claim 5, wherein:

the hold time constraint error is highly sensitive to the waveform error when input slew rate of the cell type is small.

7. The computer-implemented method of claim 1, further comprising:

identifying a cell as risky if the waveform error at a pin of the cell exceeds the threshold on the waveform error and/or the hold time constraint error for the type of the cell according to the DRC table.

8. The computer-implemented method of claim 1, further comprising:

re-optimizing the identified risky cells in the IC design via a timing engineering change order (timing ECO).

9. The computer-implemented method of claim 1, further comprising:

re-optimizing the identified risky cells in the IC design by adopting low threshold voltage (VT) cells in place of high VT cells.

10. The computer-implemented method of claim 1, further comprising:

re-optimizing the identified risky cells in the IC design by refining transition constraints of the cells to reduce the waveform error and/or the hold time constraint error of the cells.

11. A system for design rule checking (DRC) during static timing analysis (STA) of an integrated circuit (IC) design, comprising:

a computing device programmed with executable instructions that, when executed;

analyze cells with distorted waveforms in a cell library and generate both library-based and simulated waveforms for each cell type according to a plurality of parameters for the cell type;

construct a lookup table based on analysis of the distorted waveforms, wherein the lookup table maps waveform error to hold time constraint error of each cell type in the library and is saved in a memory;

identify one or more cells in the IC design as risky for timing constraint violation during static timing analysis of the IC design according to the lookup table;

re-optimize the identified risky cells to reduce risk for timing violation of the IC design.

12. The system of claim 11, wherein:

the plurality of parameters for the cell type include process, voltage, and temperature (PVT) set during fabrication, cell type, input slew, and output loading of the cell type.

13. The system of claim 11, wherein:

the computing device is programmed with executable instructions that, when executed, distort the waveforms by one or more of distortion delay and starting voltage of waveform distortion.

14. The system of claim 11, wherein:

the computing device is programmed with executable instructions that, when executed, measure the waveform error as an enclosed area between the library-based and simulated waveforms of the cell type.

15. The system of claim 11, wherein:

the computing device is programmed with executable instructions that, when executed, establish a relationship between the waveform error and the constraint error of the cell type via linear regression.

16. The system of claim 11, wherein:

the computing device is programmed with executable instructions that, when executed, identify a cell as risky if the waveform error at a pin of the cell exceeds the threshold on the waveform error and/or the hold time constraint error for the type of the cell according to the DRC table.

17. The system of claim 11, wherein:

the computing device is programmed with executable instructions that, when executed, re-optimize the identified risky cells in the IC design via a timing engineering change order (timing ECO).

18. The system of claim 11, wherein:

the computing device is programmed with executable instructions that, when executed, re-optimize the identified risky cells in the IC design by adopting low threshold voltage (VT) cells in place of high VT cells.

19. The system of claim 11, wherein:

the computing device is programmed with executable instructions that, when executed, re-optimize the identified risky cells in the IC design by refining transition constraints of the cells to reduce the waveform error and/or the hold time constraint error of the cells.

20. At least one non-transitory computer-readable storage medium having computer-executable instructions embodied thereon, wherein, when executed by at least one processor, the computer-executable instructions cause the at least one processor to:

analyze cells with distorted waveforms in a cell library and generate both library-based and simulated waveforms for each cell type according to a plurality of parameters for the cell type;

construct a lookup table based on analysis of the distorted waveforms, wherein the lookup table maps waveform error to hold time constraint error of each cell type in the library;

identify one or more cells in the IC design as risky for timing constraint violation during static timing analysis of the IC design according to the lookup table;

re-optimize the identified risky cells to reduce risk for timing violation of the IC design.