RECONFIGURABLE PROCESSING UNIT

• US 20150170021A1
• Filed: 12/18/2013
• Published: 06/18/2015
• Est. Priority Date: 12/18/2013
• Status: Active Grant

• Current Assignee: Tahoe Research Limited (f/k/a Learndale Limited) (Vector Capital Corporation)
• Original Assignee: Intel Corporation
• Inventors: Lupon, Marc, Herrero Abellanas, Enric, Latorre, Fernando, Lopez, Pedro, Falcon, Ayose, Pratas, Frederico
• Granted Patent: US 9,978,014 B2
• Time in Patent Office: Days
• US Class Current: 1/1
• CPC Class Codes: G06N 3/045 Combinations of networks
• CPC Class Codes: G06N 3/063 using electronic means

Abstract

A processing device includes a processor core and a number of calculation modules that each is configurable to perform any one of operations for a convolutional neuron network system. A first set of the calculation modules are configured to perform convolution operations, a second set of the calculation modules are reconfigured to perform averaging operations, and a third set of the calculation modules are reconfigured to perform dot product operations.

Claims

1. A processing device, comprising:

a processor core; and

a plurality of calculation circuits that each is configurable by the processor core to perform any one of operations of a convolutional neuron network (CNN) system.

2. The processing device of claim 1, wherein the operations of the CNN system comprise convolution operation, averaging operation, maximum value operation, and dot product operation.

3. The processing device of claim 1, wherein the operations of the CNN system comprise convolution operation, averaging operation, and a maximum value operation.

4. The processing device of claim 1, further comprising an interconnect through which the processor core is coupled to the plurality of calculation circuits.

5. The processing device of claim 1, wherein the processor core and the calculation circuits are part of a processor block.

6. The processing device of claim 1, wherein a first set of the plurality of calculation circuits are configured to perform convolution operations, a second set of the plurality of calculation circuits are configured to perform averaging operations, and a third set of the plurality of calculation circuits are configured to perform dot product operations.

7. The processing device of claim 1, wherein the plurality of calculation circuits are configured to perform a first operation, and subsequently, the plurality of calculation circuits are reconfigured to perform a second operation.

8. The processing device of claim 1, wherein the plurality of calculation circuits are configured to perform 8-bit operations.

9. The processing device of claim 1, wherein the plurality of calculation circuits are configured to perform operations at a higher precision than 8 bits.

10. The processing device of claim 1, wherein the plurality of calculation circuits each comprises a reconfigurable distribution module, a set of multipliers, and a reconfigurable accumulation module.

11. The processing device of claim 10, wherein the plurality of calculation circuits each comprises four multipliers.

12. The processing device of claim 10, wherein the reconfigurable distribution module is to distribute input signals, kernel parameters, and weight parameters to inputs of the set of multipliers, wherein the set of multipliers are to generate respective products of the inputs of the set of multipliers, and wherein the reconfigurable accumulation module is to compute a sum of the respective products of the inputs of the set of multipliers.

13. The processing device of claim 1, wherein the CNN system comprises at least one convolution layer performing convolution operations, at least one pooling layer performing averaging operations, and a fully-connected neuron network performing dot product operations.

14. A method, comprising:

receiving, by a processor, input values;

configuring a first set of calculation circuits coupled to the processor to a first configuration to perform any one of operations of a first stage of a convolutional neuron network (CNN) system;

configuring a second set of the calculation circuits coupled to the processor to a second configuration to perform any one of operations of a second stage of the CNN system; and

transmitting the input values to the first and second sets of the calculation circuits to perform the operations of the first and second stages of the CNN system.

15. The method of claim 14, wherein the operations of the CNN system comprise convolution operation, averaging operation, maximum value operation, and dot product operation.

16. The method of claim 14, wherein the operations of the CNN system comprise convolution operation, averaging operation, and a maximum value operation.

17. The method of claim 14, further comprising:

configuring a third set of calculation circuits coupled to the processor to a third configuration to perform any one of operations of a third stage of the CNN system; and

transmitting the input values to the first, second and third sets of calculation circuits to perform operations of the first, second and third stages of the CNN system,

wherein the first stage comprises convolution operation, the second stage comprises averaging operation, and the third stage comprises dot product operation.

18. The method of claim 14, further comprising:

configuring the plurality of calculation circuits to perform a first operation; and

reconfiguring the plurality of calculation circuits to perform a second operation.

19. The method of claim 14, wherein the plurality of calculation circuits are configured to perform 8-bit operations.

20. The method of claim 14, wherein the plurality of calculation circuits are configured to perform operations at higher precision than 8 bits.

21. The method of claim 14, wherein the calculation circuits each comprises a reconfigurable distribution module, a set of multipliers, and a reconfigurable accumulation module.

22. A system on a chip (SoC), comprising:

a plurality of reconfigurable processing unit each of which is configurable by a processor to perform any one of operations of a convolutional neuron network (CNN) system at any one of precisions.

23. The SoC of claim 22, wherein the operations of the CNN system comprise convolution operation, averaging operation, maximum value operation and dot product operation.

24. The SoC of claim 22, further comprising an interconnect coupled between the plurality of reconfigurable processing units and the processor.